Abstract
This paper proposes test design architecture suitable for built-in self-testing (BIST) of embedded cores-based digital circuits by using a reconfigurable device. In the paper, a sample circuit under test (CUT) and its corresponding space compressor were realized in Java language, downloaded, and then tested at runtime in a simulation environment written in JBits.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Das, S.R., Ramamoorthy, C.V., Assaf, M.H., Petriu, E.M., Jone, W.-B.: Fault Tolerance in Systems Design in VLSI Using Data Compression Under Constraints of Failure Probabilities. IEEE Trans. Instrum. Meas. 50, 1725–1747 (2001)
Bardell, P.H., McAnney, W.H., Savir, J.: Built-In Test for VLSI: Pseudorandom Techniques. Wiley Interscience, New York (1987)
Jone, W.-B., Das, S.R.: Space Compression Method for Built-In Self-Testing of VLSI Circuits. Int. J. Comput. Aided VLSI Des. 3, 309–322 (1991)
Karpovsky, M., Nagvajara, P.: Optimal Robust Compression of Test Responses. IEEE Trans. Comput. C-39, 138–141 (1990)
Lee, H.K., Ha, D.S.: On the Generation of Test Patterns for Combinational Circuits. Tech. Rep. 12-93, Dept. Elec. Eng., Virginia Polytec. Inst. and State Univ., Blacksburg, VA (1993)
Li, Y.K., Robinson, J.P.: Space Compression Method with Output Data Modification. IEEE Trans. Comput. Aided Des. 6, 290–294 (1987)
McCluskey, E.J.: Built-In Self-Test Techniques. IEEE Des. Test Comput. 2, 21–28 (1985)
Pomeranz, I., Reddy, L.N., Reddy, S.M.: COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits. In: Proc. Int. Test Conf., pp. 194–203 (1991)
Pradhan, D.K., Gupta, S.K.: A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. IEEE Trans. Comput. C-40, 743–763 (1991)
Reddy, S.M., Saluja, K., Karpovsky, M.G.: Data Compression Technique for Test Responses. IEEE Trans. Comput. C-37, 1151–1156 (1988)
Saluja, K.K., Karpovsky, M.: Testing Computer Hardware Through Compression in Space and Time. In: Proc. Int. Test Conf., pp. 83–88 (1983)
Savir, J.: Reducing the MISR Size. IEEE Trans. Comput. C-45, 930–938 (1996)
Chakrabarty, K.: Test Response Compaction for Built-In Self-Testing. Ph.D. Dissertation, Dept. Comp. Sc. Eng., Univ. Michigan, Ann Arbor, MI (1995)
Pouya, B., Touba, N.A.: Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. In: Proc. VLSI Test Symp., pp. 70–77 (1998)
Rajsuman, R.: System-on-a-Chip: Design and Test. Artech House, Boston, MA (2000)
JBits SDK, http://www.xilinx.com/products/jbits/
Xilinx: Inc.: The Programmable Logic Data Book (1999)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Assaf, M.H. et al. (2004). Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment. In: Das, G., Gulati, V.P. (eds) Intelligent Information Technology. CIT 2004. Lecture Notes in Computer Science, vol 3356. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30561-3_33
Download citation
DOI: https://doi.org/10.1007/978-3-540-30561-3_33
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-24126-3
Online ISBN: 978-3-540-30561-3
eBook Packages: Computer ScienceComputer Science (R0)