Abstract
We present here a real time stereo matching chip which is based on a general trellis form with vergent optical axis. The architecture can deal with general axis angle of cameras with better resolution in given space. For a pair of images with M × N pixels, only \(\mathcal{O}(MN)\) time is required. The design is highly scalable and fully exploits the concurrent and configurable nature of the algorithm. We implement stereo chip on Xilix FPGA with 208 PEs(Processing Elements) that can obtain disparity range of 208 levels. It can provide the real-time stereo matching for the mega-pixel images.
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© 2004 Springer-Verlag Berlin Heidelberg
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Jeong, H., Park, S. (2004). Generalized Trellis Stereo Matching with Systolic Array. In: Cao, J., Yang, L.T., Guo, M., Lau, F. (eds) Parallel and Distributed Processing and Applications. ISPA 2004. Lecture Notes in Computer Science, vol 3358. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30566-8_32
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DOI: https://doi.org/10.1007/978-3-540-30566-8_32
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-24128-7
Online ISBN: 978-3-540-30566-8
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