Skip to main content
SpringerLink
Log in

Testing Deadlock-Freeness in Real-Time Systems: A Formal Approach

  • Conference paper
Formal Approaches to Software Testing (FATES 2004)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3395))

Included in the following conference series:

Abstract

A Time Action Lock is a state of a Real-time system at which neither time can progress nor an action can occur. Time Action Locks are often seen as signs of errors in the model or inconsistencies in the specification. As a result, finding out and resolving Time Action Locks is a major task for the designers of Real-time systems. Verification is one of the methods of discovering deadlocks. However, due to state explosion, the verification of deadlock freeness is computationally expensive. The aim of this paper is to present a computationally cheap testing method for Timed Automata models and pointing out any source of possible Time Action Locks to the designer.

We have implemented the approach presented in the paper, which is based on the geometry of Timed Automata, via a Testing Tool called TALC (Time Action Lock Checker). TALC, which is used in the conjunction with the model checker UPPAAL, tests the UPPAAL model and provides feedback to the designer. We have illustrated our method by applying TALC to a model of a simple communication protocol.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Alur, R., Dill, D.L.: A Theory for Timed Automata. Theoretical Computer Science 125, 183–235 (1994)

    Article  MathSciNet  MATH  Google Scholar 

  2. Amnell, T., Behrmann, G., Bengtsson, J., D’Argenio, P.R., David, A., Fehnker, A., Hune, T., Jeannet, B., Larsen, K.G., Möller, M.O., Pettersson, P., Weise, C., Yi, W.: UPPAAL—Now, Next and Future. In: Cassez, F., Jard, C., Rozoy, B., Dermot, M. (eds.) MOVEP 2000. LNCS, vol. 2067, pp. 100–125. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  3. Amon, T., Borriello, G., Hu, T., Liu, J.: Symbolic Timing Verification of Timing Diagrams Using Presburger Formulas. In: 34th ACM/IEEE Design Automation Conference (DAC) (June 1997)

    Google Scholar 

  4. Barett, C.W., Dill, D.L., Levitt, J.R.: Validity Checking for Combinations of Theories with Equality. LNCS, vol. 818, pp. 187–201. Springer, Heidelberg (1996)

    Google Scholar 

  5. Bengtsson, J., Griffioen, W.O.D., Kristoffersen, K.J., Larsen, K.G., Larsson, F., Pettersson, P., Yi, W.: Verification of an Audio Protocol with Bus Collision Using UPPAAL. In: Alur, R., Henzinger, T.A. (eds.) CAV 1996. LNCS, vol. 1102, pp. 244–256. Springer, Heidelberg (1996)

    Chapter  Google Scholar 

  6. Bengtsson, J., Larsen, K.G., Larsson, F., Pettersson, P., Yi, W.: UPPAAL, a Tool suite for automatic verification of Real-time systems. In: Alur, R., Sontag, E.D., Henzinger, T.A. (eds.) HS 1995. LNCS, vol. 1066, pp. 232–243. Springer, Heidelberg (1996)

    Chapter  Google Scholar 

  7. Bornot, S., Sifakis, J.: On the composition of hybrid systems. In: Henzinger, T.A., Sastry, S.S. (eds.) HSCC 1998. LNCS, vol. 1386, pp. 49–63. Springer, Heidelberg (1998)

    Chapter  Google Scholar 

  8. Bowman, H.: Time and action lock freedom properties of timed automata. In: Kim, M., Chin, B., Kang, S., Lee, D. (eds.) Formal Techniques for Networked and Distributed Systems, pp. 119–134. Kluwer Academic Publishers, Dordrecht (2001)

    Google Scholar 

  9. Bowman, H., Faconti, G., Massink, M.: Specification and verification of media constraints using UPPAAL. In: Markopoulos, Johnos, P. (eds.) Proceedings of Design, Specification and Verification of Interactive Systems 1998, pp. 261–277. Springer, Heidelberg (1998)

    Google Scholar 

  10. Bultan, T., Gerber, R., Pugh, W.: Symbolic Model Checking of Infinite State Programs Using Presburger Arithmetic. In: Grumberg, O. (ed.) CAV 1997. LNCS, vol. 1254, pp. 400–411. Springer, Heidelberg (1997)

    Chapter  Google Scholar 

  11. Bourbaki, N.: Elements of Mathematics —General Topology, Ch. 1-4. Springer, Heidelberg (1980)

    Google Scholar 

  12. eXtensible Markup Language (XML), http://www.w3.org/XML/

  13. Ferrante, J., Rackoff, C.: A Deicision Procedure for the first Order Theory of Real Addition with order. SIAM Journal of Computation 4, 69–76 (1975)

    Article  MATH  Google Scholar 

  14. Finkel, A., Leroux, J.: How to compose Presburger-accelerations: Applications to broadcast protocols. In: Agrawal, M., Seth, A.K. (eds.) FSTTCS 2002. LNCS, vol. 2556, pp. 145–156. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  15. Havelund, K., Skou, A., Larsen, K.G., Lund, K.: Formal Modelling and Analysis of an Audio/Video Protocol: An Industrial Case Study Using UPPAA. In: Proceedings of the 18th IEEE Real-Time Systems Symposium, pp. 2–13 (1997)

    Google Scholar 

  16. Henzinger, T.A.: Sooner is Safer Than Later. Inf. Process. Lett. 43(3), 135–141 (1992)

    Article  MathSciNet  MATH  Google Scholar 

  17. Higashino, T., Nakata, A., Taniguchi, K., Cavalli, A.R.: Generating Test Cases for a Timed I/O Automaton Model. In: Proceedings of the Twelfth IFIP Workshop on Testing of Communicating Systems (IWTCS 1999), pp. 197–214 (1999)

    Google Scholar 

  18. Apache Jakarta Project, Common digester, http://jakarta.apache.org/commons/digester/

  19. Kreisel, G., Krivine, J.: Elements of Mathematical Logic; Model Theory. North-Holland Publishing Company, Amsterdam (1967)

    MATH  Google Scholar 

  20. Lönn, H., Pettersson, P.: Formal Verification of a TDMA Protocol Start-Up Mechanism. In: Proceedings of 1997 IEEE Pacific Rim International Symposium on Fault-Tolerant Systems, pp. 235–242 (1997)

    Google Scholar 

  21. Larsen, K.G., Pettersson, P., Yi, W.: UPPAAL in a Nutshell. Springer International Journal of Software Tools for Technology Transfer 1(1+2) (1997)

    Google Scholar 

  22. Milner, R.: Communication and concurrency. Prentice Hall, Upper Saddle River (1989)

    MATH  Google Scholar 

  23. The Omega Project, http://www.cs.umd.edu/projects/omega/

  24. Shibata, N., Okano, K., Higashino, T., Taniguchi, K.: A decision algorithm for prenex normal form rational Presburger sentences based on combinatorial geometry. In: Proceedings of the 2nd International Conf. on Discrete Mathematics and Theoretical Computer Science and the 5th Australasian Theory Symposium (DMTCS 1999+CATS 1999), pp. 344–359 (1999)

    Google Scholar 

  25. Shiple, T.R., Kukula, J.H., Ranjan, R.K.: A Comparison of Presburger Engines for EFSM Reachability. LNCS, vol. 1427, p. 280. Springer, Heidelberg (1998)

    Google Scholar 

  26. Gruntz, D., Murer, S., Szyperski, C.: Component Software - Beyond Object-Oriented Programming, 2nd edn. Addison-Wesley, Reading (2002)

    Google Scholar 

  27. Tripakis, S.: Verifying Progress in Timed Systems. In: Katoen, J.-P. (ed.) AMAST-ARTS 1999, ARTS 1999, and AMAST-WS 1999. LNCS, vol. 1601, p. 299. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  28. Wang, F., Hwang, G., Yu, F.: TCTL Inevitability Analysis of Dense-Time Systems. In: Ibarra, O.H., Dang, Z. (eds.) CIAA 2003. LNCS, vol. 2759, pp. 176–187. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. University of Birmingham, UK

    Behzad Bordbar

  2. Osaka University, Japan

    Kozo Okano

Authors
  1. Behzad Bordbar
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kozo Okano
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. University of Goettingen, Germany

    Jens Grabowski

  2. Department of Computer Science, Aalborg University, Fredrik Bajersvej 7E, DK-9220, Aalborg, Denmark

    Brian Nielsen

Rights and permissions

Reprints and permissions

Copyright information

© 2005 IFIP International Federation for Information Processing

About this paper

Cite this paper

Bordbar, B., Okano, K. (2005). Testing Deadlock-Freeness in Real-Time Systems: A Formal Approach. In: Grabowski, J., Nielsen, B. (eds) Formal Approaches to Software Testing. FATES 2004. Lecture Notes in Computer Science, vol 3395. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-31848-4_7

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-31848-4_7

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-25109-5

  • Online ISBN: 978-3-540-31848-4

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation