This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J.A. Bondy and U.S.R. Murty. Graph Theory with Applications, American El- sevier, 1976
J.A. Brzozowski. Delay-Insensitivity and Ternary Simulation, Theoretical Computer Science, 245 (2000) 3-25.
J.A. Brzozowski and J.C. Ebergen. Recent Developments in the Design of Asynchronous Circuits, Proc. Fundamentals of Computation Theory, (J. Csirik, J. Demetrovics and F. Gécseg, eds.), Springer-Verlag, Berlin, 1989, 78-94.
J.A. Brzozowski and J.C. Ebergen. On the Delay-Sensitivity of Gate Networks, IEEE Trans. on Computers, 41, 11 (1992), 1349-1360.
J.A. Brzozowski and Z. Esik. Hazard Algebras, Formal Methods in System Design, 23, 3 (2003), 223-256.
J.A. Brzozowski, Z. Ésik and Y. Iland. Algebras for Hazard Detection, Beyond Two - Theory and Applications of Multiple-Valued Logic , (M. Fitting, and E. Orlowska, eds.), Physica-Verlag, Heidelberg, 2003, 3-24.
J.A. Brzozowski and M. Gheorghiu. Gate Circuits in the Algebra of Transients, Theoretical Informatics and Applications, to appear.
J.A. Brzozowski, S. Hauck and C-J. Seger, Design of Asynchronous Circuits, Chapter 15 in [10]
J.A. Brzozowski and C-J. Seger. A Characterization of Ternary Simulation of Gate Networks, IEEE Trans. Computers, C-36, 11 (1987), 1318-1327.
J.A. Brzozowski and C-J. Seger. Asynchronous Circuits, Springer, Berlin, 1995.
J.A. Brzozowski and M. Yoeli. Digital Networks, Prentice-Hall, 1976
J.A. Brzozowski and M. Yoeli. On a Ternary Model of Gate Networks, IEEE Trans. on Computers, C-28, 3 (1979), 178-183.
J.A. Brzozowski and H. Zhang. Delay-Insensitivity and Semi-Modularity, Formal Methods in System Design, 16, 2 (2000), 187-214.
T.J. Chaney and C.E. Molnar. Anomalous Behavior of Synchronizer and Arbiter Circuits, IEEE Trans. on Computers, C-22, 4 (1973), 421-422.
D.L. Dill. Trace Theory for Automatic Hierarchical Verification of SpeedIndependent Circuits, PhD Thesis, Computer Science Department, Carnegie Mellon University, February 1988. Also, The MIT Press, Cambridge, MA, 1989.
J.C. Ebergen. Translating Programs into Delay-Insensitive Circuits, PhD Thesis, Department of Mathematics and Computing Science, Eindhoven University of Technology, Eindhoven, The Netherlands, October 1987. Also, CWI Tract 56, Centre for Math. and Computer Science, Amsterdam, The Netherlands, 1989.
J.C. Ebergen. A Formal Approach to Designing Delay-Insensitive Circuits, Dis- tributed Computing, 5, 3 (1991), 107-119.
E.B. Eichelberger. Hazard Detection in Combinational and Sequential Switching Circuits, IBM J. Res. and Dev., 9 (1965), 90-99.
M. Gheorghiu. Circuit Simulation Using a Hazard Algebra , MMath Thesis, Dept. of Computer Science, University of Waterloo, Waterloo, ON, Canada, 2001. http://maveric.uwaterloo.ca/publication.html
M. Gheorghiu and J.A. Brzozowski. Simulation of Feedback-Free Circuits in the Algebra of Transients, Int. J. Foundations of Computer Science , 14, 6 (2003), 1033-1054.
J. He, M.B. Josephs and C.A.R. Hoare. A Theory of Synchrony and Asynchrony, Programming Concepts and Methods, (M. Broy and C.B. Jones, eds.), NorthHolland, Amsterdam, 1990, 459-478.
M.B. Josephs and J.T. Udding. An Algebra for Delay-Insensitive Circuits, Computer-Aided Verification, (E.M. Clarke and R.P. Kurshan, eds.), AMSACM, Providence, RI, 1990, 147-175.
C.A.R. Hoare. Communicating Sequential Processes, Prentice-Hall, Inc., Engle- wood Cliffs, NJ, 1985.
D.A. Huffman. The Design and Use of Hazard-Free Switching Circuits, J. ACM, 4 (1957),47-62.
A.J. Martin. Compiling Communicating Processes into Delay-Insensitive VLSI Circuits, Distributed Computing, 1 (1986), 226-234.
E.J. McCluskey. Transient Behavior of Combinational Logic Circuits, Redundancy Techniques for Computing Systems, (R.H. Wilcox and W.C. Mann, eds.), Spartan Books, Washington, DC, 1962, 9-46.
C. Mead and L. Conway. Introduction to VLSI Systems, Addison-Wesley, Read- ing, MA, 1980
R.E. Miller. Switching Theory, Volume II: Sequential Circuits and Machines, Wiley, New York, 1965.
C.E. Molnar, T.P. Fang and F.U. Rosenberger. Synthesis of Delay-Insensitive Modules, Proc. 1985 Chapel Hill Conference on VLSI, (H. Fuchs, ed.), Computer Science Press, Rockville, Maryland, 1985, 67-86.
M. Mukaidono. Regular Ternary Logic Functions—Ternary Logic Functions Suitable for Treating Ambiguity, Proc. 13th Ann. Symp. on Multiple-Valued Logic, 1983, 286-291.
D.E. Muller. A Theory of Asynchronous Circuits, Tech. Report 66, Digital Computer Laboratory, University of Illinois, Urbana-Champaign, Illinois, USA, 1955.
D.E. Muller and W.S. Bartky. A Theory of Asynchronous Circuits, Proc. Int. Symp. on the Theory of Switching, Annals of the Computation Laboratory of Harvard University, Harvard University Press, 1959, 204-243.
R. Negulescu. Process Spaces and Formal Verification of Asynchronous Circuits, PhD Thesis, Dept. of Computer Science, University of Waterloo, Waterloo, ON, Canada, 1998.
H. Schols. A Formalisation of the Foam Rubber Wrapper Principle, Master’s Thesis, Department of Mathematics and Computing Science, Eindhoven University of Technology, Eindhoven, The Netherlands, February 1985.
C-J.H. Seger. Ternary Simulation of Asynchronous Gate Networks, MMath Thesis, Dept. of Comp. Science, University of Waterloo, Waterloo, ON, Canada, 1986.
C-J.H. Seger. Models and Algorithms for Race Analysis in Asynchronous Cir- cuits, PhD Thesis, Dept. of Comp. Science, University of Waterloo, Waterloo, ON, Canada, 1988.
C-J.H. Seger. On the Existence of Speed-Independent Circuits, Theoretical Com- puter Science, 86, 2 (1991), 343-364.
C.E. Shannon. A Symbolic Analysis of Relay and Switching Circuits, Trans. AIEE, 57 (1938), 713-723.
S. Silver. True Concurrency in Models of Asynchronous Circuit Behaviors, MMath Thesis, Dept. of Computer Science, University of Waterloo, Waterloo, ON, Canada, 1998.
S. Silver and J.A. Brzozowski. True Concurrency in Models of Asynchronous Circuit Behavior, Formal Methods in System Design, 22, 3 (2003), 183—203.
I.E. Sutherland and J. Ebergen. Computers without Clocks, Scientific American, August 2002, 62-69.
J.T. Udding. Classification and Composition of Delay-Insensitive Circuits, PhD Thesis, Department of Mathematics and Computing Science, Eindhoven University of Technology, Eindhoven, The Netherlands, September 1984.
J.T. Udding. A Formal Model for Defining and Classifying Delay-Insensitive Circuits and Systems, Distributed Computing, 1, 4 (1986), 197-204.
S.H. Unger. Hazards and Delays in Asynchronous Sequential Switching Circuits, IRE Trans. on Circuit Theory, CT-6 (1959), 12-25.
S.H. Unger. Asynchronous Sequential Switching Circuits, Wiley-Interscience, New York, 1969.
K. van Berkel. Handshake Circuits, Cambridge University Press, Cambridge, England, 1993.
J.L.A. van de Snepscheut. Trace Theory and VLSI Design, PhD Thesis, Department of Computing Science, Eindhoven University of Technology, Eindhoven, The Netherlands, May 1983. Also, Lecture Notes in Computer Science, vol. 200, Springer-Verlag, Berlin, 1985
T. Verhoeff. A Theory of Delay-Insensitive Systems, PhD Thesis, Department of Mathematics and Computing Science, Eindhoven University of Technology, Eindhoven, The Netherlands, May 1994.
H. Zhang. Delay-Insensitive Networks, MMath Thesis, Dept. of Computer Science, University of Waterloo, Waterloo, ON, Canada, 1997.
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
(2006). Janusz Brzozowski. In: Esik, Z., Martín-Vide, C., Mitrana, V. (eds) Recent Advances in Formal Languages and Applications. Studies in Computational Intelligence, vol 25. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-33461-3_2
Download citation
DOI: https://doi.org/10.1007/978-3-540-33461-3_2
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-33460-6
Online ISBN: 978-3-540-33461-3
eBook Packages: EngineeringEngineering (R0)