Abstract
Software pipelining techniques have been shown to significantly improve the performance of loop-intensive scientific programs. The Itanium architecture contains many features to enhance parallel execution, such as support for efficient software pipelining of loops. The drawback of software pipelining is the high register requirements, which may lead to software pipelining failure due to limited static general registers in Itanium. This paper evaluates the register requirements of software-pipelined loops. It then presents a novel register allocation scheme, which allocates stacked registers to serve as static registers. Experimental results show that this method gains an average 2.4% improvement, and a peak 18% improvement in performance on NAS Benchmarks.
This work was supported by NSFC grant 60173010.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Dehnert, J.C., Hsu, P.Y., Bratt, J.P.: Overlapped Loop Support in the Cydra 5. In: Proceedings of ASPLOS 1989, pp. 26–38 (1989)
Allan, V.H., Jones, R.B., Lee, R.M., Allan, S.J.: Software Pipelining. ACM Computing Surveys 27, 367–432 (1995)
Huff, R.A.: Lifetime-sensitive modulo scheduling. In: Proceedings of PLDI 1993, pp. 58–267 (1993)
Llosa, J.: Reducing the Impact of Register Pressure on Software Pipelining. PhD thesis. Universitat Politècnica de Catalunya (1996)
Rau, B.R., Lee, M., Tirumalai, P., Schlansker, P.: Register allocation for software pipelined loops. In: Proceedings of PLDI 1992, pp. 283–299 (1992)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lin, H., Li, W., Tang, Z. (2003). Overcoming Static Register Pressure for Software Pipelining in the Itanium Architecture. In: Zhou, X., Xu, M., Jähnichen, S., Cao, J. (eds) Advanced Parallel Processing Technologies. APPT 2003. Lecture Notes in Computer Science, vol 2834. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39425-9_12
Download citation
DOI: https://doi.org/10.1007/978-3-540-39425-9_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20054-3
Online ISBN: 978-3-540-39425-9
eBook Packages: Springer Book Archive