Abstract.
Instruction-Level Parallelism (ILP) is the main source of performance achievable in numerical applications. Architecturalresources and program recurrences are the main limitations to the amount of ILP exploitable from loops, the most time-consuming part in numerical computations. In order to increase the issue rate, current designs use growing degrees of resource replication for memory ports and functional units. But the high costs in terms of power, area and clock cycle of this technique are making it less attractive.
Clustering is a popular technique used to decentralize the design of wide issue cores and enable them to meet the technology constraints in terms of cycle time, area and power. Another approach is using wide functional units. These techniques reduce the port requirements in the register file and the memory subsystem, but they have scheduling constraints which may reduce considerably the exploitable ILP.
This paper evaluates several VLIW designs that make use of both techniques, analyzing power, area and performance, using loops belonging to the Perfect Club benchmark. From this study we conclude that applying either clustering, widening or both on the same core yields very power-efficient configurations with little area requirements.
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Pericás, M., Ayguadé, E., Zalamea, J., Llosa, J., Valero, M. (2003). Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. In: Veidenbaum, A., Joe, K., Amano, H., Aiso, H. (eds) High Performance Computing. ISHPC 2003. Lecture Notes in Computer Science, vol 2858. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39707-6_9
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DOI: https://doi.org/10.1007/978-3-540-39707-6_9
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