Abstract
The goal of this paper is to present a new technique to reduce power-consumption in circuits with detection of computation completion (asynchronous circuits) by adding delay elements in paths of the circuit. The aim of these new elements is to decrease the number of switchings of those gates placed in the logic cone of the delay element due to the computation completion before those gates receive the new incoming values. We have studied this approach for a set of benchmarks (LGSynth95) and evaluated the trade-off between power-consumption reduction and performance degradation.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Baena, C., Juan-Chico, J., Bellido, M.J., Ruiz de Clavijo, P., Jiménez, C.J., Valencia, M.: Measurement of the switching activity of cmos digital circuits at gate level. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds.) PATMOS 2002. LNCS, vol. 2451, pp. 353–362. Springer, Heidelberg (2002)
van Berkel, C.H., Josephs, M.B., Nowick, S.M.: Scanning the technology: Applications of asynchronous circuits. Proceedings of the IEEE 87(2), 223–233 (1999)
van Berkel, K., Burgess, R., Kessels, J., Peeters, A., Roncken, M., Schalij, F.: Asynchronous circuits for low power: A DCC error corrector. IEEE Design & Test of Computers 11(2), 22–32 (1994)
Hauck, S.: Asynchronous design methodologies: An overview. Proceedings of the IEEE 83(1), 69–93 (1995)
Kearney, D.: Theoretical limits on the data dependent Performance of asynchronous circuits. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 1999, pp. 201–207 (1999)
Martin, A.J.: Asynchronous datapaths and the design of an asynchronous adder. Formal Methods in System Design 1(1), 119–137 (1992)
Najm, F.N.: A survey of power estimation techniques in vlsi circuits. IEEE Transactions on VLSI Systems 2(4), 446–455 (1994)
Nanya, T.: Challenges to dependable asynchronous processor design. In: Sasao, T. (ed.) Logic Synthesis and Optimization, ch. 9, pp. 191–213. Kluwer Academic Publishers, Dordrecht (1993)
Nowick, S.M., Yun, K.Y., Beerel, P.A.: Speculative completion for the design of high-performance asynchronous dynamic adders. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 210–223. IEEE Computer Society Press, Los Alamitos (1997)
Storto, M., Saletti, R.: Time-multiplexed dual-rail protocol for lowpower delay-insensitive asynchronous communication. In: Trullemans- Anckaert, A.-M., Sparsø, J. (eds.) Power and Timing Modeling, Optimixation and Simulation (PATMOS), October 1998, pp. 127–136 (1998)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
López, S., Garnica, Ó., Hidalgo, I., Lanchares, J., Hermida, R. (2003). Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_17
Download citation
DOI: https://doi.org/10.1007/978-3-540-39762-5_17
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
Online ISBN: 978-3-540-39762-5
eBook Packages: Springer Book Archive