Abstract
In this paper, we compare the current de-facto standard high-speed family (self-resetting domino logic) with the most promising recently proposed ones: dynamic current mode logic, gate diffusion input logic and race logic architecture. For this purpose, we have used an 8-bit array multiplier in the 0.13 um TSMC CMOS process whose critical path is representative of many modern complex ICs. Each design adopts solely one logic style and it has been optimized with a standard industrial semi-custom flow. As metrics of comparison we have used speed and the energy (E), energy-per-time (ET) and energy-per-time-square (ET2) metrics. The comparison shows that self-resetting domino logic is the best choice when only speed is of concern, while dynamic current mode logic should be the preferred approach for all other cases. The other logic families failed to live up with their original promises of high-performance.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Bernstein, K., Carrig, K.M., Durham, C.M., Hansen, P.R., Hogenmiller, D., Nowak, E.J., Rohrer, N.J.: High Speed CMOS Design Styles. Kluwer Academic Publishers, Dordrecht (1999)
Woo, A.K.: Static PLA or ROM Circuit with Self-Generated Precharge. U.S. Patent # 4, 728, 827 (March 1, 1988)
Hwang, W., Gristede, G.D., Sanda, P., Wang, S.Y., Heidel, D.F.: Implementation of a Self-Resetting CMOS 64-Bit Parallel Adder with Enhanced Testability. IEEE Journal of Solid-State Circuits 34(8) (August 1999)
Allam, M.W., Elmasry, M.I.: Dynamic Current Mode Logic (DyCML): A New Low- Power High-Performance Logic Style. IEEE Journal of Solid-State Circuits 36(3) (March 2001)
Somasekhar, D., Roy, K.: Differential Current Switch Logic: A Low Power DCVS Logic Family. IEEE Journal of Solid-State Circuits 31(7) (July 1996)
Morgenshtein, A., Fish, A., Wagner, I.A.: Gate-Diffusion Input (GDI) – A Novel Power Efficient Method for Digital Circuits: A Design Methodology. In: ASIC/SOC Conference 2001, Proceedings. 14th Annual IEEE International (2001)
Lee, S.J., Yoo, H.J.: Race Logic Architecture (RALA): A Novel Logic Concept Using the Race Scheme of Input Variables. IEEE Journal of Solid-State Circuits 37(2) (February 2002)
Martin, A.J.: Towards an energy complexity of computation. Information processing Letters 77 (2001)
Gonzalez, R., Gordon, B., Horowitz, M.: Supply and threshold voltage scaling for low power CMOS. IEEE Journal of Solid-State Circuits 32(8) (August 1997)
Weste, N.H.E., Eshragian, K.: Principle of CMOS design: a system perspective. Addison-Wesley, Reading (1993)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Privitera, G., Pessolano, F. (2003). Analysis of High-Speed Logic Families. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_2
Download citation
DOI: https://doi.org/10.1007/978-3-540-39762-5_2
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
Online ISBN: 978-3-540-39762-5
eBook Packages: Springer Book Archive