Abstract
In this paper we present a genetic approach for the efficient generation of an encoder to minimize switching activity on the high-capacity lines of a communication bus. The approach is a static one in the sense that the encoder is realized ad hoc according to the traffic on the bus. The approach refers to embedded systems in which it is possible to have detailed knowledge of the trace of the patterns transmitted on a bus following execution of a specific application. The approach is compared with the most efficient encoding schemes proposed in the literature on both multiplexed and separate buses. The results obtained demonstrate the validity of the approach, which on average saves up to 50% of the transitions normally required.
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References
Benini, L., De Micheli, G., Macii, E., Poncino, M., Quer, S.: Power optimization of core-based systems by address bus encoding. IEEE Transactions on Very Large Scale Integration 6(4) (December 1998)
Benini, L., De Micheli, G., Macii, E., Sciuto, D., Silvano, C.: Asymptotic zero-transition activity encoding for address busses in low power microprocessor-based systems. In: Great Lakes Symposium VLSI, Urbana, IL, March 1997, pp. 77–82 (1997)
Benini, L., De Micheli, G., Macii, E., Sciuto, D., Silvano, C.: Address bus encoding techniques for system-level power optimization. In: IEEE Design Automation and Test Conference in Europe, Paris, France, February 1998, pp. 861–866 (1998)
Henkel, J., Lekatsas, H., Jakkula, V.: Encoding schemes for address busses in energy efficient SOC design. In: VLSI-SOC 2001 11th International Conference of Very Large Scale Integration, Montpellier, France (December 2001)
Mazumder, P., Rudnick, E.M.: Genetic Algorithms for VLSI Design, Layout & Test Automation. Prentice Hall, Inc., Englewood Cliffs (1999)
International thechnology roadmap for semiconductors. Semiconductor Industry Association (1999)
Stan, M.R., Burleson, W.P.: Bus invert coding for low power I/O. IEEE Transactions on VLSI Systems 3, 49–58 (1995)
Su, C., Tsui, C., Despain, A.: Saving power in the control path of embedded processors. IEEE Design and Test of computers 11(4), 24–30 (1994)
West, N.H., Eshraghian, K.: Principles of CMOS VLSI Design. Addison-Wesley, Reading (1998)
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© 2003 Springer-Verlag Berlin Heidelberg
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Ascia, G., Catania, V., Palesi, M. (2003). A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_4
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DOI: https://doi.org/10.1007/978-3-540-39762-5_4
Publisher Name: Springer, Berlin, Heidelberg
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