Abstract
We study a power reduction method for the asynchronous dual-rail bus. A preliminary analysis of data communication patterns between a processor and a memory module reveals that many communications deliver a set of data items repeatedly. To exploit such communication characteristics, a frequent value cache(FVC) method is proposed that delivers not always data itself but sometimes an index of data item of FVC. Because of the lower switching activity, FVC reduces the power consumption of the asynchronous dual-rail bus. Simulation results illustrate that FVC reduces the power consumption of the normal asynchronous dual-rail bus by 25% and 30% at maximum for integer and floating-point benchmarks, respectively.
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Choi, BS., Lee, DI. (2003). Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_58
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DOI: https://doi.org/10.1007/978-3-540-39762-5_58
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