Abstract
In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (Central Processor Unit), MCU (Micro Controller Unit), cache, and et cetera. This paper introduces a new low-power cache controller with successive tag comparison algorithm. Using these methods, the power consumption of a cache can be reduced. Simulation results show that the power consumption of a cache using the proposed method is reduced by 42% compared with conventional methods.
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Kim, TC., Kim, C., Chung, BY., Kim, SW. (2003). Low-Power Cache with Successive Tag Comparison Algorithm. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_66
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DOI: https://doi.org/10.1007/978-3-540-39762-5_66
Publisher Name: Springer, Berlin, Heidelberg
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