Abstract
In this paper, the design of an embedded FPGA architecture (i.e. configurable logic blocks) is presented and a complete tool-supported design flow starting from architecture level (i.e. RT-level) and ending with the derivation of the reconfiguration bitstream for the FPGA programming is introduced. The proposed design flow consists of new and modified and extended academic tools. In particular, new tools were developed in order to complement certain critical steps in the implementation flow, since existing academic tools do not combine for a cohesive and complete flow. The remaining design steps are implemented by modified existing academic tools. The FPGA architecture and the tool development is an interactive task, depending on what architectures can be supported by the tools. Using this design support tool set, we designed and simulated in 0.18 TSMC technology an FPGA architecture. More specifically, the detailed design characteristics of the Configurable Logic Block Architecture as well as the interconnect network are determined. Finally, experimental results in terms of energy consumption and delay are given.
This work was partially supported by the project IST-34793-AMDREL which is funded by the E.C.
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References
Compton, K., Hauck, S.: Reconfigurable Computing: A Survey of Systems and Software. ACM Computing Surveys 34(2), 171–210 (2002)
Betz, V., Rose, J.: VPR: A New Packing, Placement and Routing Tool for FPGA Research. In: Glesner, M., Luk, W. (eds.) FPL 1997. LNCS, vol. 1304, pp. 213–222. Springer, Heidelberg (1997)
UCLA
http://www.eecg.toronto.edu/~jayar/software/edif2blif/edif2blif.html
Sentovich, M., Singh, K.J., Lavagno, L., et al.: SIS: A System for Sequential Circuit Synthesis. UCB/ERL M92/41 (1992)
Betz, V., Rose, J.: Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size. In: IEEE Custom Integrated Circuits Conference, Santa Clara, CA, 551-554 (1997)
Ahmed, E., Rose, J.: The effect of LUT and cluster size on deep-submicron FPGA performance and density. In: FPGA 2000, pp. 3-12 (2000)
Poon, K.K.W.: Power Estimation for Field-Programmable Gate Arrays. Master of Applied Science Dissertation, University of British Columbia (2002)
Betz, V., Rose, J.: Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency. IEEE Transactions on VLSI Systems, 445—456 (1998)
Betz, V., Rose, J.: FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. In: ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 59–68 (1999)
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Tatas, K. et al. (2003). FPGA Architecture Design and Toolset for Logic Implementation. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_67
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DOI: https://doi.org/10.1007/978-3-540-39762-5_67
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