Abstract
In this work we present different hardware implementations of a multi-layer perceptron for speech recognition. The designs have been defined using two different abstraction levels: register transfer level (VHDL) and a higher algorithmic-like level (Handel-C). The implementations have been developed and tested into a reconfigurable hardware (FPGA) for embedded systems. A study of the two considered approaches costs (silicon area), speed and required computational resources is presented.
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© 2003 Springer-Verlag Berlin Heidelberg
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Ortigosa, E.M., Ortigosa, P.M., Cañas, A., Ros, E., Agís, R., Ortega, J. (2003). FPGA Implementation of Multi-layer Perceptrons for Speech Recognition. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_117
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DOI: https://doi.org/10.1007/978-3-540-45234-8_117
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