Abstract
Pulsed neural networks can be applied to the design of dense arrays using minimum hardware resources in the interconnection among neurons. Using statistical saturation in pulse frequency coded neurons, a minimum size hardware neuron can be implemented. The proposed neuron is compact enough to be included in large arrays. The presented architecture has additional interesting characteristics like unrestricted topology and scalability. In this paper, the design and implementation of a high density spiking neural array is presented.
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References
Schoenauer, T., Atasoy, S., Mehrtash, N., Klar, H.: Simulation of a Digital Neuro-Chip for Spiking Neural Networks. In: International Joint Conference on Neural Networks (IJCNN), Como, Italy (July 2000)
Schaefer, M., Schoenauer, T., Wolff, C., Hartmann, G., Klar, H., Rueckert, U.: Simulation of Spiking Neural Networks - Architectures and Implementations, Neurocomputing. Elsevier, Amsterdam (2001)
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© 2003 Springer-Verlag Berlin Heidelberg
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Xicotencatl, J.M., Arias-Estrada, M. (2003). FPGA Based High Density Spiking Neural Network Array. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_118
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DOI: https://doi.org/10.1007/978-3-540-45234-8_118
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