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FPGA Implementation of the Adaptive Lattice Filter

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Field Programmable Logic and Application (FPL 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2778))

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Abstract

The paper presents the FPGA implementation of a noise canceler with an adaptive RLS-Lattice filter in the Xilinx devices. Since this algorithm requires floating-point computations, Logarithmic Numbering System (LNS) has been used. The pipelined lattice filter macro and input/output conversion routines has been designed. The implementation results are compared with an implementation on 32-bit IEEE floating point signal processor.

Jirí Kadlec: This work has been partially suported by the Ministry of Education of the Czech Republic under Project LN00B096 and from EU Project RECONF2 (IST-2001-34016).

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References

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Authors and Affiliations

  1. Department of Signal Processing, Institute of Information Theory and Automation, CAS, Pod vodárenskou vezí 4, 182 08, Prague 8, Czech Republic

    Antonín Heřmánek, Zdeněk Pohl & Jiří Kadlec

Authors
  1. Antonín Heřmánek
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  2. Zdeněk Pohl
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  3. Jiří Kadlec
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Editor information

Editors and Affiliations

  1. Department of Electrical and Electronic Engineering, Imperial College London, Exhibition Road, SW7 2BT, London, UK

    Peter Y. K. Cheung

  2. Department of Electrical & Electronic Engineering, Imperial College London, Exhibition Road, SW7 2BT, London, UK

    George A. Constantinides

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© 2003 Springer-Verlag Berlin Heidelberg

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Heřmánek, A., Pohl, Z., Kadlec, J. (2003). FPGA Implementation of the Adaptive Lattice Filter. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_128

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  • DOI: https://doi.org/10.1007/978-3-540-45234-8_128

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-40822-2

  • Online ISBN: 978-3-540-45234-8

  • eBook Packages: Springer Book Archive

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