Abstract
We discuss high-performance programmable asynchronous pipeline arrays (PAPAs). These pipeline arrays are coarse-grain field programmable gate arrays (FPGAs) that realize high data throughput with fine-grain pipelined asynchronous circuits. We show how the PAPA architecture maintains most of the speed and energy benefits of a custom asynchronous design, while also providing post-fabrication logic reconfigurability. We report results for a prototype PAPA design in a 0.25μm CMOS process that has a peak pipeline throughput of 395MHz for asynchronous logic.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Cummings, U.V., Lines, A.M., Martin, A.J.: An Asynchronous Pipeline Latticestructure Filter. In: Proc. Int’l Symp. on Asynchronous Circuits and Systems (1994)
Hauck, S., Burns, S., Borriello, G., Ebeling, C.: An FPGA for implementing asynchronous circuits. IEEE Design & Test of Computers 11(3), 60–69 (1994)
Ho, Q.T., et al.: Implementing asynchronous circuits on LUT based FPGAs. In: Proc. 12th Int’l Conf. on Field Programmable Logic and Applications (2002)
How, D.L.: A Self Clocked FPGA for General Purpose Logic Emulation. In: Proc. of the IEEE 1996 Custom Integrated Circuits Conf. (1996)
Keller, E.: Building Asynchronous Circuits with JBits. In: Proc. 11th Int’l Conf. on Field Programmable Logic and Applications (2001)
Konishi, R., et al.: PCA-1: A fully asynchronous self-reconfigurable LSI. In: Proc. 7th Int’l Symp. on Asynchronous Circuits and Systems (2001)
Lines, A.M.: Pipelined Asynchronous Circuits. M.S. Thesis, California Institute of Technology (1996)
Maheswaran, K.: Implementing Self-Timed Circuits in Field Programmable Gate Arrays. M.S. Thesis, U.C. Davis (1995)
Manohar, R., Martin, A.J.: Slack Elasticity in Concurrent Computing. In: Proc. of the 4th Int’l Conf. on the Mathematics of Program Construction (1998)
Manohar, R.: A Case for Asynchronous Computer Architecture. In: Proc. of the ISCA Workshop on Complexity-Effective Design (2000)
Martin, A.J.: Compiling Communicating Processes into Delay-insensitive VLSI circuits. Distributed Computing 1(4) (1986)
Martin, A.J.: The Limitations to Delay-Insensitivity in Asynchronous Circuits. In: Sixth MIT Conf. on Advanced Research in VLSI (1990)
Martin, A.J., Lines, A., Manohar, R., et al.: The Design of an Asynchronous MIPS R3000. In: Proc. of the 17th Conf. on Advanced Research in VLSI (1997)
Payne, R.: Asynchronous FPGA architectures. IEE Computers and Digital Techniques 143(5), 282–286 (1996)
Teifel, J., Fang, D., Biermann, D., Kelly, C., Manohar, R.: Energy-Efficient Pipelines. In: Proc. 8th Int’l Symp. on Asynchronous Circuits and Systems (2002)
Traver, C., Reese, R.B., Thornton, M.A.: Cell Designs for Self-timed FPGAs. In: Proc. of the 2001 ASIC/SOC Conf. (2001)
Tsu, W., et al.: HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array. In: Proc. 7th Int’l Symp. on Field-Programmable Gate Arrays (1999)
Williams, T.E.: Self-Timed Rings and their Application to Division. Ph.D. thesis, Stanford University (1991)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Teife, J., Manohar, R. (2003). Programmable Asynchronous Pipeline Arrays. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_34
Download citation
DOI: https://doi.org/10.1007/978-3-540-45234-8_34
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40822-2
Online ISBN: 978-3-540-45234-8
eBook Packages: Springer Book Archive