Abstract
In this article we present a model of coarse grained reconfigurable architecture, dedicated to accelerate data-flow oriented applications. The proliferation of new academic and industrial architectures implies a large variety of solutions for platform-based designers. Thus, efficient metrics to compare and qualify these architectures are more and more necessary. Several metrics, Troughput Density [3][12], Remanence [4] and Operative Density are then used to perform comparisons on different architectures. Architectures are often customisable and purpose several parameters. Therefore, it is crucial to characterize the architectural model according to these parameters. This paper proposes as a case study the Systolic Ring, and gives a set of metrics as functions of the architecture parameters. The methodology illustrated is generic and proved very efficient to highlight architectural properties such as the scalability.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Mangione-Smith, W.H., et al.: Seeking Solutions in Configurable Computing. IEEE Computer, 38–43 (December 1997)
Grünbacher, H., Hartenstein, R.W.: The Roadmap to Reconfigurable Computing. FPL 2000. LNCS, vol. 1896. Springer, Heidelberg (2000)
DeHon, A.: Comparing Computing Machines. In: Configurable Computing: Technology and Applications. In: Proc. SPIE, November 2-3, vol. 3526 (1998)
Sassatelli, G., et al.: Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP applications. In: IEEE Design Automation and Test in Europe (DATE 2002), Paris, France, March 2002, pp. 553–557 (2002)
Sassatelli, G.: Architectures reconfigurables dynamiquement pour les systèmes sur puce., Ph.D. thesis, Université Montpellier II, France (April 2002)
Demigny, D., et al.: La rémanence des architectures reconfigurables, un critère significatif des architectures. In: Proc. of JFAAA, Monastir, Tunisie, December 2002, pp. 49–52 (2002)
Xilinx, the Programmable Logic Data Book (2000)
Demigny, D., et al.: Architecture à reconfiguration dynamique pour le traitement temps réel des images. Techniques et Science de l’Information Numéro Spécial Architectures Reconfigurables 18(10), 1087–1112 (1999)
David, R., et al.: DART: A Dynamically Reconfigurable Architecture dealing with Next Generation Telecommunications Constraints. In: 9th IEEE Reconfigurable Architecture Workshop RAW (April 2002)
Singh, H., et al.: MorphoSys: An Integrated Re-configurable Architecture. In: Proc. of the NATO RTO Symposium on System Concepts and Integration, Monterey, USA, avril (1998)
TMS320C62X Image/Video Processing library Programmer’s Reference (March 2000), http://www.ti.com
Wirthlin, M.J., Hutchings, B.L.: Improving Functional Density Using Run-Time Circuit Reconfiguration. IEEE Transactions On Very Large Scale Integration (VLSI) Systems 6, 247–256 (1998)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Benoit, P., Sassatelli, G., Torres, L., Robert, M., Cambon, G., Demigny, D. (2003). A Novel Approach for Architectural Models Characterization. An Example through the Systolic Ring. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_70
Download citation
DOI: https://doi.org/10.1007/978-3-540-45234-8_70
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40822-2
Online ISBN: 978-3-540-45234-8
eBook Packages: Springer Book Archive