Abstract
A new architecture for calculating the addition/subtraction function required in a logarithmic number system (LNS) is presented. A substantial logic saving over previous works is illustrated along with similarities with the dual-path floating-point addition method. The new architecture constrains the lookups to be of fractional width and uses shifting to achieve this. Instead of calculating the function \(\log_2(1\pm2^{M-K})\) in two lookups the function arithmetic is performed (i.e. the two functions 2M −  K and log2( ), plus a correction function) as this allows logic sharing that maps well to FPGA. Better-than-floating-point (BTFP) accuracy is used to enable a future comparison with floating-point.
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Lee, B., Burgess, N. (2003). A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_78
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DOI: https://doi.org/10.1007/978-3-540-45234-8_78
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