Abstract
In this paper, a modular reconfigurable architecture for efficient stuck-at fault simulation in digital circuits is described. The architecture is based on a Universal Faulty Gate Block, which models each 2-input gate by a 4-input Look-Up Table (LUT) and a Shift-Register (SR) with 3 stages, and relies on collapsing the stuck-at fault list of the gates using equivalence and dominance relations between faults. An example is presented, the expected performance is estimated and the applicability and limitations of the architecture are discussed.
This work was developed under the EC MEDEA+ A503 ASSOCIATE project, with funding from the Portuguese Government Agency "Agência de Inovação".
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Abramovici, M., Breuer, M., Friedman, A.: Digital Systems Testing and Testable Design. IEEE Computer Society Press, Los Alamitos (1990)
Fujiwara, H.: Logic Testing and Design for Testability. MIT Press, Cambridge (1985)
Abramovici, M., Levendel, Y., Menon, P.: A logic simulation machine. In: Proc. 19th Design Automation Conference, pp. 65–73 (1982)
Pfister, G.: The Yorktown Simulation Engine. In: Proc. 19th Design Automation Conference, pp. 51–54 (1982)
Abramovici, M., Menon, P.: Fault simulation on reconfigurable hardware. In: 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM 1997) (1997)
Abramovici, M., Saab, D.G.: Satisfiability on Reconfigurable Hardware. In: 7th Int. Workshop on Field Programmable Logic and Applications (1997)
Suyama, T., Yokoo, M., Sawada, H.: Solving Satisfiability Problems Using Logic Synthesis and Reconfigurable Hardware. In: 31st Hawaii Intl. Conf. on Sys. Sciences (1998)
Zhong, P., Martonosi, M., Ashar, P., Malik, S.: Accelerating Boolean Satisfiability with Configurable Hardware. In: Proc. IEEE Symp. on Field-Programmable Custom Computing Machines (April 1998)
Abramovici, M., de Sousa, J., Saab, D.: A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. In: Design Automation Conference (DAC 1999), New Orleans, USA (1999)
Kocan, F., Saab, D.G.: Concurrent D-Algorithm on Reconfigurable Hardware. In: Int. Conference on Computer Aided Design (ICCAD 1999) (1999)
Plessl, C., Platzner, M.: Instance-Specific Accelerators for Minimum Covering. In: 1st Intl. Conf. on Eng. of Reconf. Systems and Algorithms, Las Vegas, USA (2001)
Cheng, K.-T., Huang, S.-H., Dai, W.-J.: Fault Emulation: a New Methodology for Fault Grading. IEEE Trans. CAD 18(10), 1487–1495 (1999)
Parreira, A., Teixeira, J., Santos, M.: A Novel Approach to FPGA-Based Hardware Fault Modeling and Simulation. In: IEEE Int. Workshop on Design and Diag. of Elect. Circ. and Systems, Poland (April 2003)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Augusto, J.S., Almeida, C.B., Neto, H.C.C. (2003). A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_79
Download citation
DOI: https://doi.org/10.1007/978-3-540-45234-8_79
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40822-2
Online ISBN: 978-3-540-45234-8
eBook Packages: Springer Book Archive