Abstract
This paper presents a fault simulation algorithm and that uses efficient partial reconfiguration of FPGAs. The methodology is particularly useful for evaluation of BIST effectiveness, and for applications in which multiple fault injection is mandatory, such as safety-critical applications. A novel fault collapsing methodology is proposed, which efficiently leads to the minimal stuck-at fault list at the look-up-tables’ terminals. Fault injection is performed using local partial reconfiguration with small binary files. Our results on the ISCAS’89 sequential circuit benchmarks show that our methodology can be orders of magnitude faster than software or fully reconfigurable hardware fault simulation..
This work has been partially funded by FCT (Portugal), POCTI/ESE41788/2001.
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Parreira, A., Teixeira, J.P., Pantelimon, A., Santos, M.B., de Sousa, J.T. (2003). Fault Simulation Using Partially Reconfigurable Hardware. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_81
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DOI: https://doi.org/10.1007/978-3-540-45234-8_81
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