Avoiding Conventional Overheads in Parallel Logic Simulation: A New Architecture

Abstract

Logic simulation is an important tool in VLSI design. The size of current VLSI circuits is increasing dramatically the computational effort demanded of this design tool. Parallel Processing techniques have reduced computational time. While processing speed is a crucial factor, equally important is the range of delay models that the simulation can support. Unfortunately, some parallel methods limit the accuracy of the delay model. Other parallel methods can only achieve a modest speedup through the use of standard computational mechanisms such as Load balancing and Event-scheduling. Deadlock issues must be resolved in these systems. As the processor numbers increase these tasks grow to the detriment of processing performance. This paper introduces an Associative memory architecture for logic simulation, APPLES, which eliminates the need of conventional support tasks, attains high speedup performance and is capable of simulating complex delay models. The architecture has been implemented as a Verilog model and evaluated theoretically and on various ISCAS-85 benchmarks.