Abstract
The drive of Multi-FPGA systems has been hindered due to the low gate utilization percentages they present. The scarce inter-FPGA communication resources turn the circuit partitioning phase into a complex one. The problem is becoming more acute for mesh routing topologies since the communication between distant FPGAs increases the IO-pin consumption of intermediate FPGAs. For these topologies the integration of placement and routing phases in the partitioning process may be the natural approach to take into account all communication constraints. In this research, we have modeled the Multi-FPGA mesh topology as a large single FPGA where the borders between neighboring FPGAs are represented by a superimposed template. Then, a placement optimization based on Simulated Annealing is performed to minimize the cut-sizes on this partition template. An initial routing is updated in each placement iteration to keep account of the actual number of nets crossing between FPGAs. Two different problems, mapping onto a fixed Multi-FPGA mesh or finding the Multi-FPGA mesh that fits best for a given circuit, can be treated. This second problem has been solved for a set of benchmark circuits. A large cut-size reduction has been achieved for all circuits being sufficient to get a high gate utilization percentage in some cases.
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de Vicente, J., Lanchares, J., Hermida, R. (1999). Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_10
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DOI: https://doi.org/10.1007/978-3-540-48302-1_10
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