Abstract
On-chip storage has become critical in large FPGAs. This has led most FPGA vendors to include configurable embedded arrays in their devices. Because of the large number of ways in which the arrays can be combined, and because of the configurability of each array, there are often many ways to implement the memories required by a circuit. Implementing user memories using physical arrays is called logical-to-physical mapping, and has previously been studied for single-port FPGA memory arrays. Most current FPGAs, however, contain dual-port arrays. In this paper, we present a logical-to-physical algorithm that specifically targets dual-port FPGA arrays. We show that this algorithm results in 28% denser memory implementations than the only previously published algorithm.
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© 1999 Springer-Verlag Berlin Heidelberg
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Ho, W.K.C., Wilton, S.J.E. (1999). Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_12
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DOI: https://doi.org/10.1007/978-3-540-48302-1_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66457-4
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