Abstract
The paper addresses the problem of mapping an application specified as a task graph on a heterogeneous architecture which contains a software processor, a dynamically reconfigurable hardware coprocessor and memory elements. The problem comprises of three sub-problems: partitioning of tasks between hardware and software, assigning tasks mapped on hardware to different temporal segments and scheduling task execution, reconfiguration of hardware, inter-processor and intra-processor communication. We present a heuristic based technique for solving the problem. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm and experimentation with synthetic graphs.
This work was partially supported by the ARPA RASSP program and US-AF, Wright Lab, under contract numbers F33615-93-C-1316 and F33615-97-C-1043 respectively.
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© 1999 Springer-Verlag Berlin Heidelberg
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Chatha, K.S., Vemuri, R. (1999). Hardware-Software Codesign for Dynamically Reconfigurable Architectures. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_18
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DOI: https://doi.org/10.1007/978-3-540-48302-1_18
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