Abstract
We present a new switch block for FPGAs with segmented routing architectures. We show that the new switch block outperforms all previous switch blocks over a wide range of segmented architectures in terms of area, with virtually no impact on speed. For segments of length four, our switch block results in an FPGA with 13% fewer transistors in the routing fabric.
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© 1999 Springer-Verlag Berlin Heidelberg
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Masud, M.I., Wilton, S.J.E. (1999). A New Switch Block for Segmented FPGAs. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_28
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DOI: https://doi.org/10.1007/978-3-540-48302-1_28
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66457-4
Online ISBN: 978-3-540-48302-1
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