Abstract
This paper studies pipelined multiplication techniques for implementation on FPGAs with emphasis on the utilisation of FPGA hardware resource. Performance of multiplier implementations are measured for commercially available FPGA architectures where two inherent issues are introduced and investigated. These being the imbalance of critical interconnect delay between general routing and static carry interconnects, and the amount of FPGA logic area used and its poor utilisation. For each of these issues suggestions are proposed and investigated.
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References
Burns, J., Donlin, A., Hoggs, J., Singh, S., de Wit, M.: A dynamic reconfiguration run-time system. In: FPGAs for Custom Computing Machines (April 1997)
Haynes, S.D., Cheung, P.Y.K.: A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure. In: FPGAs for Custom Computing Machines (April 1998)
Hwang, K.: Computer Arithmetic: Principles, Architecture, and Design. John Wiley and Sons, Chichester (1979)
Hwang, K.: Advanced Computer Architecture: Parallelism, Scalability, Programmability. McGraw-Hill, New York (1993)
Xilinx Incorporated. Xilinx XC4000 data sheet (1996)
Mintzer, L.: FIR filters with field-programmable gate arrays. Journal of VLSI Signal Processing 6(2), 119–127 (1993)
Slous, B., Kean, T., New, B.: A multiplier for the XC6200. In: Sixth International Workshop on Field Programmable Logic and Appications (1996)
ALTERA Corporation. FLEX 10000 data sheet (June 1996)
Wallace, C.S.: A suggestion for fast multipliers. IEEE Transactions on Electronic Computers EC-13, 4–17 (1964)
Wojko, M., ElGindy, H.: Self configurable binary multipliers for LUT addressable FPGAs. In: Shardi, T. (ed.) Proceedings of PART 1998, Newcastle, New South Wales, Australia, September 1998. Springer, Heidelberg (1998)
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Wojko, M. (1999). Pipelined Multipliers and FPGA Architectures. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_36
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DOI: https://doi.org/10.1007/978-3-540-48302-1_36
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66457-4
Online ISBN: 978-3-540-48302-1
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