Abstract
This paper describes integer multiplier design optimizations for FPGA technology. The changes in partial product generator component enable to infer CLB fast carry logic for building Wallace trees. This change increases speed and gives better resource allocation.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Patterson, D.A., Hennessy, J.L. (eds.): Computer Architecture. A qualitative. Morgan Kaufmann Publishers, Inc., San Francisco (1996)
Põldre, J., Tammemäe, K., Mandre, M.: Modular Exponent Realization on FPGAs. In: Proceedings of FPL 1998 (1988)
Synopsys Module Compiler User Guide. Synopsys, Inc., ver. 1998.08 (1988)
Keating, M.: Pierre Bricaud Reuse Methodology. Manual Kluwer Academic Publishers, Dordrecht (1998)
Product Specification. Virtex 2.5V. Xilinx, Inc. (November 1998)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Põldre, J., Tammemäe, K. (1999). Reconfigurable Multiplier for Virtex FPGA Family. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_38
Download citation
DOI: https://doi.org/10.1007/978-3-540-48302-1_38
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66457-4
Online ISBN: 978-3-540-48302-1
eBook Packages: Springer Book Archive