Logic Circuit Speeding up through Multiplexing

Abstract

Discrete devices speeding up is the actual aspect of logic design. The combinational circuit delay essentially depends on the number of levels involved. To reduce the number of circuit levels as well as its delay a multiplexing-based technique is proposed. At first, a given Boolean function (more precisely, its SOP) is represented in partially orthogonalized form: SOP=k ₁ (SOP ₁)+k ₂(SOP ₂)+ ... +k _r (SOP _r ), where the factor-products  k ₁,...,k _r are orthogonal to each other, and  k ₁ +k ₂ + ... +k _r ≡ 1. Then this Boolean function is implemented through multiplexing of the subcircuits corresponding to SOP _i , i =1, ..., r. Switching of these subcircuits carries out by three-state gates, controlled by mutually orthogonal factor-products  k _i , i =1, ..., r. The decrease of delay is achieved by calculating of the SOP _i and k _i in parallel and thanks to an ordinary wired joint of the subcircuit outputs instead of using the multi-input OR. The method suggested is focused on the speeding up of some critical circuit path in conditions then wired OR is impermissible.