A Wildcarding Mechanism for Acceleration of Partial Configurations

Abstract

Wildcarding is a hardware feature specifically intended to accelerate the configuration process by reducing the number of configuration items required, and programming cells which share the same configuration simultaneously. In order to ascertain which cells can be programmed together, wildcarding has to be built into the address decoding hardware. In the Xilinx XC6200 series, wildcarding operates prior to decoding on bit positions of the target address. In this paper, we consider an alternative scheme, where wildcarding operates after address decoding, allowing individual cells to be addressed. This is shown to be beneficial for accelerating partial configurations where constant propagation is used to give new configurations at run-time, whilst supporting more configuration geometries than the current wildcarding mechanism.