Abstract
Field Programable Gate Arrays (FPGAs) begin to show better performance than microprocessors in many application areas because of drastic improvement of the size and speed. In the near future, FPGAs will be directly attached to or involved in microprocessors as accelerators that execute algorithms written in programming languages. In this paper, we show hardware implementation techniques (multi-thread execution and speculative execution) for recursive calls and loops, which are the most time exhaustive parts in many application programs written in programming languages. These techniques can be employed with very little overheads in clock cycle speed and circuit size. Experiments on simple combinatorial problems show 4.1 – 6.7 times of speedup compared with a workstation (Ultra-Sparc 200MHz).
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© 1999 Springer-Verlag Berlin Heidelberg
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Maruyama, T., Takagi, M., Hoshino, T. (1999). Hardware Implementation Techniques for Recursive Calls and Loops. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_52
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DOI: https://doi.org/10.1007/978-3-540-48302-1_52
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66457-4
Online ISBN: 978-3-540-48302-1
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