Abstract
The cross-bar is the fastest switching architecture for multiprocessor system, yet the most expensive in terms of hardware cost. The hardware complexity is of order O(n 2 w) wheren is the number of processors and w is width of the data path. In this paper we present a novel reconfigurable architecture where the hardware cost isreducedto O(w(n/k) 2) while maintaining the same operating speedmost of the time, k is the reduction factor. The approach bases on a cache-likeconnectivity table . This table controls the reconfigurable data path of the cross bar. A hit in the connectivity table results in a direct connection of unit delay while a miss result in a miss penalty for updating the connectivity table. We assume that the local and spatial locality principles are applicable for this class of switching networks.
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© 1999 Springer-Verlag Berlin Heidelberg
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Caohuu, T., Le, T.T., Glesner, M., Becker, J. (1999). Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_61
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DOI: https://doi.org/10.1007/978-3-540-48302-1_61
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