A Reconfigurable Architecture for High Speed Computation by Pipeline Processing

Abstract

We propose a new reconfigurable architecture for high speed computation by pipeline processing. In this architecture, computations by the operation units and data transfer between the operation units are executed in different clock cycles (in pipeline) in order to achieve high clock speed, and the operation units and the data transfers are controlled by 32 bit width in order to reduce the size of the configuration data for high speed dynamic reconfiguration. The cache memories support cache block size read/write operations in order to realize high memory bandwidth. The expected speedup by this architecture in some simple tree search problems (combinatorial problems) is 34 – 41 times compared with a microprocessor of same clock cycle speed.