Memory Access Optimization and RAM Inference for Pipeline Vectorization

Abstract

This paper describes memory access optimization in the context of pipeline vectorization, a method for synthesizing hardware pipe- lines in reconfigurable systems from software program loops. Since many algorithms for reconfigurable coprocessors are I/O bound, the throughput of the coprocessor is determined by the external memory accesses. Thus access optimizations directly improve the system’s performance. Two kinds of optimizations have been studied. First, we consider methods for reducing the number of accesses based on saving frequently-used data in on-chip storage. In particular, recent FPGAs provide on-chip RAM which can be used for this purpose. We present RAM inference, a technique which automatically extracts small on-chip RAMs to reduce external memory accesses. Second, we aim to minimize the time spent on external accesses by scheduling as many accesses in parallel as possible. This optimization only applies to architectures with multiple memory banks. We present a technique which allocates program arrays to memory banks, thereby minimizing the overall access time.

This work is supported by a European Union training project financed by the Commission in the TMR programme, the UK Engineering and Physical Sciences Research Council, Embedded Solutions Ltd., and Xilinx Inc.