Tabu Search: Ultra-Fast Placement for FPGAs

Abstract

Two-dimensional placement is an important problem for FPGAs. Current FPGA capacity allows one million gate equivalent designs. As FPGA capacity grows, new innovative approaches will be required for efficiently mapping circuits to FPGAs. We propose to use the tabu search optimization technique for the physical placement step of the circuit mapping process. Our goal is to reduce the execution time of the placement step while providing high quality placement solutions. In this paper we present a study of tabu search applied to the physical placement problem. First we describe the tabu search optimization technique. Then we outline the development of a tabu search based technique for minimizing the total wire length and minimizing the length of critical path edges for placed circuits on FPGAs. We demonstrate our methodology with several benchmark circuits available from MCNC, UCLA, and other universities. Our tabu search technique has shown dramatic improvement in placement time relative to commercially available CAE tools (20×), and it results in placements of quality similar to that of the commercial tools.