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Parallel Implementation of Cholesky LL T-Algorithm in FPGA-Based Processor

  • Conference paper
Parallel Processing and Applied Mathematics (PPAM 2007)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4967))

Abstract

The fixed-size processor array architecture, which is intended for realization of matrix LL T-decomposition based on Cholesky algorithm, is proposed. In order to implement this architecture in modern FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed. The AU is intended for configuring in the Xilinx Virtex4 FPGAs, and its hardware complexity is much less than the complexity of similar AUs operating with floating-point numbers.

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Author information

Authors and Affiliations

  1. Technical University of Koszalin, ul. Sniadeckich 2, 75-453, Koszalin, Poland

    Oleg Maslennikow

  2. National Technical University of Ukraine, pr.Peremogy 37, 03056, Kiev, Ukraine

    Volodymyr Lepekha & Anatoli Sergiyenko

  3. Czestochowa University of Technology, ul. Dabrowskiego 69, 42-200, Czestochowa, Poland

    Adam Tomas & Roman Wyrzykowski

Authors
  1. Oleg Maslennikow
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  2. Volodymyr Lepekha
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  3. Anatoli Sergiyenko
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  4. Adam Tomas
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  5. Roman Wyrzykowski
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Editor information

Roman Wyrzykowski Jack Dongarra Konrad Karczewski Jerzy Wasniewski

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Maslennikow, O., Lepekha, V., Sergiyenko, A., Tomas, A., Wyrzykowski, R. (2008). Parallel Implementation of Cholesky LL T-Algorithm in FPGA-Based Processor. In: Wyrzykowski, R., Dongarra, J., Karczewski, K., Wasniewski, J. (eds) Parallel Processing and Applied Mathematics. PPAM 2007. Lecture Notes in Computer Science, vol 4967. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-68111-3_15

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  • DOI: https://doi.org/10.1007/978-3-540-68111-3_15

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-68105-2

  • Online ISBN: 978-3-540-68111-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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