Inter-processor Communication Optimization in Dynamically Reconfigurable Embedded Parallel Systems

Abstract

The paper concerns program design methods for a new kind of parallel embedded systems in which communication infrastructure is dynamically run-time adaptable to particular application program needs. The new system architecture assumes a fairly large number of autonomous communication links in each executive processor. Inter-processor link connections are subdue to dynamic reconfiguration according to the compile-time elaborated strategy based on the application program graph analysis. Automatic program structuring methods are used for defining the structuring of reconfigurable processor link sets which enables the look-ahead connection reconfiguration that overlaps with the current program execution including data communication. Algorithms for respective program task scheduling and dynamic program decomposition into sections executed with the look-ahead created connections of subsets of processor links are presented. Simulation experiment results with structuring of parallel numerical programs of matrix multiplication are presented. The experiments compare program structuring quality of the look ahead connection reconfiguration based on multiple crossbar switches with the quality of reconfiguration in a single crossbar switch but with the use of multiple link subsets reconfigured in advance.