Abstract
In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.
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References
Borre, K., Bertelsem, N., Jensen, S.H., Akos, D.M., Rinder, P.: A Software-Defined GPS and Galileo Receiver: A Single-Frequency Approach (Applied and Numerical Harmonic Analysis), 1st edn. Birkhäuser, Boston (2007)
Lodi, A., Toma, M., Campi, F., Cappelli, A., Canegallo, R., Guerrieri, R.: A VLIW processor with reconfigurable instruction set for embedded applications. IEEE Journal of Solid-State Circuits 38, 1876–1886 (2003)
Borgatti, M., Lertora, F., Foret, B., Cali, L.: A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O. IEEE Journal of Solid-State Circuits 38, 521–529 (2003)
PACT XPP Technologies: Smart Media Processor, http://www.pactxpp.com
Stretch Corporation: S5000, S6000, http://www.stretchinc.com
Enzler, R.: Architectural Trade-offs in Dynamically Reconfigurable Processors. PHD-thesis, ETH Zürich (2004)
von Sydow, T., Neumann, B., Blume, H., Noll, T.G.: Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic. In: Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (2006)
Hennessy, J., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 4th edn. Morgan Kaufmann, San Francisco (2006)
Altera Corporation: Stratix III Device Handbook, vol. 1, http://www.altera.com
George, V., Rabaey, J.M.: Low-energy FPGAs: architecture and design. Kluwer Academic Publishers, Dordrecht (2001)
CoWare Corporation: LISA Language Reference Manual, http://www.coware.com
Neumann, B., von Sydow, T., Blume, H., Noll, T. G.: Design flow for embedded FPGAs based on a flexible architecture template. In: The conference on Design, automation and test in Europe (accepted for publication, 2008)
Hewlett-Packard Development Company: CACTI 5.0, http://www.hpl.hp.com
Blume, H., Feldkämper, H., Noll, T.G.: Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. Journal of VLSI Signal Processing Systems 40, 19–34 (2005)
Noll, T.G.: Application specific eFPGAs for SoC platforms. In: International Symposion on VLSI Design, Automation and Test (2005)
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von Sydow, T., Blume, H., Kappen, G., Noll, T.G. (2008). ASIP-eFPGA Architecture for Multioperable GNSS Receivers. In: Bereković, M., Dimopoulos, N., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2008. Lecture Notes in Computer Science, vol 5114. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-70550-5_15
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DOI: https://doi.org/10.1007/978-3-540-70550-5_15
Publisher Name: Springer, Berlin, Heidelberg
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