Abstract
Processor-memory wall is always the focus of computer architecture research. While existing cache architecture can significantly mitigate the gap between processor and memory, they are not very effective in certain scenarios. For example, when scratch data is cached, it is not necessary to write back modified data. However, existing cache architectures do not provide enough support in distinguishing this kind of situation. Based on this observation, we propose a novel cache architecture called LIve Range Aware Cache (LIRAC). This cache scheme can significantly reduce cache write-backs with minimal hardware support.
The performance of LIRAC is evaluated using trace-driven analysis and simplescalar simulator. We used SPEC CPU 2000 benchmarks and a number of multimedia applications. Simulation results show that LIRAC can eliminate 21% cache write-backs on average and up to 85% in the best case.
The idea of LIRAC can be extended and used in write buffers and CMP with transactional memory. In this paper, we also propose LIve Range Aware BUFfer (LIRABuf). Simulation results show that the improvement of LIRABuf is also significant.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Wulf, W.A., McKee, S.A.: Hitting the memory wall: implications of the obvious. ACM SIGARCH Computer Architecture News 23(Issue 1 ) (1995)
Semiconductor Industry Association, International Technology Roadmap for Semiconductors (2004), http://www.itrs.net/Common/2004Update/2004Update.htm
Hammond, L., Wong, V., Chen, M., Hertzberg, B., Carlstrom, B.D., Davis, J.D., Prabhu, M.K., Wijaya, H., Kozyrakis, C., Olukotun, K.: Transactional Memory coherence and consistency. In: Proceedings of 31st Annual International Symposium on Computer Architecture (ISCA-31), pp. 102–113 (2004)
Moore, K.E., Bobba, J., Moravan, M.J., Hill, M.D., Wood, D.A.: LogTM: Logbased Transactional Memory. In: Proceedings of 12th Annual International Symposium on High Performance Computer Architecture (HPCA-12) (2006)
Gokhale, M., Holmes, W., Iobst, K.: Processing in memory: the Terasys massively parallel PIM array. IEEE Computer 28(4), 23–31 (1995)
Kozyrakis, C., Gebis, J., Martin, D., Williams, S., Mavroidis, I., Pope, S., Jones, D., Patterson, D., Yelick, K.: Vector IRAM: A Media-oriented Vector Processor with Embedded DRAM. In: 12th Hot Chips Conference, August (2000)
Wang, J., Quong, R.W.: The feasibility of using compression to increase memory system performance. In: Proc. of IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, pp. 107–113. IEEE Computer Society Press, Los Alamitos (1994)
Franklin, M., Sohi, G.S.: Register Traffic Analysis for Streamlining Inter-Operation Communication in Fine-Grain Parallel Processors. In: Proceedings of 25th International Symposium on Microarchitecture, pp. 236–245 (1992)
Luis, A., Lozano, C., Guang, R.G.: Exploiting Short-Lived Variables in Superscalar Processors. In: Proceedings of 28th International Symposium on Microarchitecture, pp. 292–302 (1995)
Savransky, G., Ronen, R., Gonzalez, A.: A Power Aware Register Management Mechanism. International Journal of Parallel Programming 31(Issue 6), 451–467 (2003)
Ponomarev, D., Kucuk, G., Ergin, O., Ghose, K.: Isolating Short-Lived Operands for Energy Reduction. IEEE Transaction on Computers 53(6), 697–709 (2004)
Martin, M.M., Roth, A., Fischer, C.N.: Exploiting Dead Value Information. In: Proceedings of 30th International Symposium on Microarchitecture, pp. 125–135 (1997)
Lepak, K.M., Bell, G.B., Lipasti, M.H.: Silent Stores and Store Value Locality. IEEE Transactions on Computers 50(11) (2001)
Chow, F., Hennessy, J.L.: Register Allocation for Priority based Coloring. In: Proceedings of the ACM SIGPLAN 84 Symposium on Compiler Constructions, pp. 222–232. ACM Press, New York (1984)
Cytron, R., Ferrante, J., Rosen, B.K., Wegman, M.N., Zadeck, F.K.: Efficiently Computing Static Single Assignment Form and the Control Dependence Graph. ACM Transactions on Programming Languages and Systems 13(4), 451–490 (1991)
Austin, T., Larson, E., Ernst, D.: SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Computer 35(2), 59–67 (2002)
Edler, J., Hill, M.D.: Dinero IV Trace-Driven Uniprocessor Cache Simulator (2003), http://www.cs.wisc.edu/~markhill/DineroIV
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer Berlin Heidelberg
About this paper
Cite this paper
Li, P., Wang, D., Wang, H., Lu, M., Zheng, W. (2007). LIRAC: Using Live Range Information to Optimize Memory Access. In: Lukowicz, P., Thiele, L., Tröster, G. (eds) Architecture of Computing Systems - ARCS 2007. ARCS 2007. Lecture Notes in Computer Science, vol 4415. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71270-1_3
Download citation
DOI: https://doi.org/10.1007/978-3-540-71270-1_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-71267-1
Online ISBN: 978-3-540-71270-1
eBook Packages: Computer ScienceComputer Science (R0)