Abstract
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP processor. We get a time triggered distributed real-time system by connecting several such ECU’s via a common bus. We define a programming model for such a system at the instruction set architecture (ISA) level and prove that it is correctly implemented at the gate level. The proof combines theories of processor correctness, communication systems, program correctness and realistic worst-case execution time (WCET) analysis into a single unified mathematical theory.
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Knapp, S., Paul, W. (2007). Realistic Worst-Case Execution Time Analysis in the Context of Pervasive System Verification. In: Reps, T., Sagiv, M., Bauer, J. (eds) Program Analysis and Compilation, Theory and Practice. Lecture Notes in Computer Science, vol 4444. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71322-7_3
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DOI: https://doi.org/10.1007/978-3-540-71322-7_3
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