Abstract
Many important algorithms in computational biology and related subjects rely on the ability to extract and to identify sub-graphs of larger graphs; an example is to find common functional structures within Protein Interaction Networks. However, the increasing size of both the graphs to be searched and the target sub-graphs requires the use of large numbers of parallel conventional CPUs. This paper proposes an architecture to allow acceleration of sub-graph identification through reconfigurable hardware, using a canonical graph labelling algorithm. A practical implementation of the canonical labelling algorithm in the Virtex-4 reconfigurable architecture is presented, examining the scaling of resource usage and speed with changing algorithm parameters and input data-sets. The hardware labelling unit is over 100 times faster than a quad Opteron 2.2GHz for graphs with few vertex invariants, and at least 10 times faster for graphs that are easier to label.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Bu, D., et al.: Topological structure analysis of the protein-protein interaction network in budding yeast. Nucleic Acids Research 31(9), 2443–2450 (2003)
Huan, J., et al.: Accurate classification of protein structural families based on coherent subgraph analysis. In: Proc. Pacific Symposium on Biocomputing (PSB), pp. 411–422 (2004)
Huan, J., Wang, W., Prins, J.: Efficient mining of frequent subgraph in the presence of isomorphism. In: Proceedings of the 3rd IEEE International Conference on Data Mining (ICDM), pp. 549–552. IEEE Computer Society Press, Los Alamitos (2003)
Kuramochi, M., Karypis, G.: Frequent subgraph dscovery. Technical Report TR-01-028, Department of Computer Science, University of Minnesota (2001)
Fortin, S.: The graph isomorphism problem. Technical Report TR-96-20, University of Alberta (1996)
McKay, B.: Practical graph isomorphism. In: Congressus Numerantium, pp. 45–87 (1981)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer Berlin Heidelberg
About this paper
Cite this paper
Thomas, D.B., Luk, W., Stumpf, M. (2007). Reconfigurable Hardware Acceleration of Canonical Graph Labelling. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2007. Lecture Notes in Computer Science, vol 4419. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71431-6_28
Download citation
DOI: https://doi.org/10.1007/978-3-540-71431-6_28
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-71430-9
Online ISBN: 978-3-540-71431-6
eBook Packages: Computer ScienceComputer Science (R0)