Abstract
This paper presented an asynchronous ARM processor employing adaptive pipeline and enhanced control schemes. This adaptive pipeline employed stage-skipping and stage-combining. The stage-skipping removed the redundant stage operations, bubbles. The stage-combining was used to unify the neighboring stage when the next stage is idle. Each stage of our implementation had several different datapaths according to the kind of instruction. The instructions in the same pipeline stage could be executed in parallel when they need different datapaths. The outputs obtained from the different datapaths were merged before the WB stage, by the asynchronous reorder buffer. We designed an ARM processor using a 0.35-μm CMOS standard cell library. In the simulation results, the processor showed approximately 2.8 times speed improvement than its asynchronous counterpart, AMULET3.
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References
Colmenar, J.M., et al.: Empiri-cal characterization of the latency of long asynchronous pipelines with data-dependent module delays. In: Proc. 12th EUROMICRO-PDP’04, Feb. 2004, pp. 311–321 (2004)
Efthymiou, A., Garside, J.D.: Adaptive pipeline structures for speculation control. In: Proc. ASYNC’03, May 2003, pp. 46–55 (2003)
Ozawa, M., et al.: A cascade ALU architecture for asynchronous super-scalar processor. IEICE Trans. Electron. E84–C(2), 229–237 (2001)
Furber, S.B., Edward, D.A., Garside, J.D.: AMULET3: A 100 MIPS asynchronous embedded processor. In: Proc. Computer Design, pp. 329–334 (2000)
Takamura, A., et al.: TITAC–2 A 32–bit scalable–delay insensitive microprocessor. In: Proc. ICCD, Oct. 1997, pp. 288–294 (1997)
Furber, S.B., et al.: AMULET2e An asynchronous embedded controller. In: Proc. ASYNC’1997, Apr. 1997, pp. 290–299 (1997)
Martin, A.J., et al.: The lutonium: sub–nanojoule asynchronous 8051 microcontroller. In: Proc. ASYNC’03, pp. 14–23 (2003)
Lee, J.-H., Kim, Y.H., Cho, K.-R.: Design of a fast asynchronous embedded CISC microprocessor, A8051. IEICE trans. on Electron. E87–C(4), 527–534 (2004)
Sima, D., Fountain, T., Kacsuk, P.: Advanced Computer Architectures: a design space approach. Addison-Wesley, Reading (1997)
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Lee, JH., Lee, SS., Cho, KR. (2007). Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2007. Lecture Notes in Computer Science, vol 4419. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71431-6_4
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DOI: https://doi.org/10.1007/978-3-540-71431-6_4
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-71430-9
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