Abstract
Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. We examine a new multilateral cache organization, replacing a conventional data cache with a set of smaller region caches that significantly reduces energy consumption with little performance impact. This is achieved by tailoring the cache resources to the specific reference characteristics of each application. In applications with small heap footprints, we save about 85% of the total cache energy. In the remaining applications, we employ a small cache for frequently accessed heap data and a larger cache for low locality data, achieving an energy savings of 80%.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Montanaro, J., et al.: A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. Digital Technical Journal 9(1), 49–62 (1997)
Geiger, M.J., McKee, S.A., Tyson, G.S.: Drowsy Region-Based Caches: Minimizing Both Dynamic and Static Power Dissipation. In: Proc. ACM International Conference on Computing Frontiers, May, pp. 378–384. ACM Press, New York (2005)
Lee, H.S., Tyson, G.S.: Region-Based Caching: An Energy-Delay Efficient Memory Architecture for Embedded Processors. In: Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, November, pp. 120–127 (2000)
Lee, H-H.S.: Improving Energy and Performance of Data Cache Architectures by Exploiting Memory Reference Characteristics. Doctoral thesis, The University of Michigan (2001)
Flautner, K., Kim, N.S., Martin, S., Blaauw, D., Mudge, T.: Drowsy Caches: Simple Techniques for Reducing Leakage Power. In: Proc. 29th International Symposium on Computer Architecture, May, pp. 147–157 (2002)
Kim, N.S., Flautner, K., Blaauw, D., Mudge, T.: Drowsy Instruction Caches: Leakage Power Reduction using Dynamic Voltage Scaling and Cache Sub-bank Prediction. In: Proc. 35th International Symposium on Microarchitecure, November, pp. 219–230 (2002)
Kim, N.S., Flautner, K., Blaauw, D., Mudge, T.: Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power. IEEE Transactions on VLSI 12(2), 167–184 (2004)
Guthaus, M.R., Ringenberg, J., Ernst, D., Austin, T., Mudge, T., Brown, R.: MiBench: A Free, Commercially Representative Embedded Benchmark Suite. In: Proc. 4th IEEE Workshop on Workload Characterization, December, pp. 3–14. IEEE Computer Society Press, Los Alamitos (2001)
Ghose, K., Kamble, M.B.: Reducing Power in Superscalar Processor Caches using Subbanking, Multiple Line Buffers and Bit-Line Segmentation. In: Proc. International Symposium on Low Power Electronics and Design, August, pp. 70–75 (1999)
Su, C-L., Despain, A.M.: Cache Designs for Energy Efficiency. In: Proc. 28th Hawaii International Conference on System Sciences, January, pp. 306–315 (1995)
Kin, J., Gupta, M., Mangione-Smith, W.H.: Filtering Memory References to Increase Energy Efficiency. IEEE Transactions on Computers 49(1), 1–15 (2000)
Lee, H.S., Ballapuram, C.S.: Energy Efficient D-TLB and Data Cache using Semantic-Aware Multilateral Partitioning. In: Proc. International Symposium on Low Power Electronics and Design, August, pp. 306–311 (2003)
Blake, R.P.: Exploring a stack architecture. IEEE Computer 10(5), 30–39 (1977)
Ditzel, D.R., McLellan, H.R.: Register Allocation for Free: The C Machine Stack Cache. In: Proc. 1st International Symposium on Architectural Support for Programming Languages and Operating Systems, March, pp. 48–56 (1982)
Berenbaum, A.D., Colbry, B.W., Ditzel, D.R., Freeman, R.D., McLellan, H.R., O’Connor, K.J., Shoji, M.: CRISP: A Pipelined 32-bit Microprocessor with 13-kbit of Cache Memory. IEEE Journal of Solid-State Circuits 22(5), 776–782 (1987)
Cho, S., Yew, P-C., Lee, G.: Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor. In: Proc. 26th International Symposium on Computer Architecture, May, pp. 100–110 (1999)
Lee, H-H.S., Smelyanskiy, M., Newburn, C.J., Tyson, G.S.: Stack Value File: Custom Microarchitecture for the Stack. In: Proc. 7th International Symposium on High Performance Computer Architecture, January, pp. 5–14 (2001)
Huang, M., Renau, J., Yoo, S.-M., Torellas, J.: L1 Data Cache Decomposition for Energy Efficiency. In: Proc. International Symposium on Low Power Electronics and Design, August, pp. 10–15 (2003)
Collins, J., Sair, S., Calder, B., Tullsen, D.M.: Pointer Cache Assisted Prefetching. In: Proc.35th IEEE/ACM International Symposium on Microarchitecture, November, pp. 62–73. ACM Press, New York (2002)
Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In: Proc. 28th International Symposium on Computer Architecture, June, pp. 240–251 (2001)
Powell, M., Yang, S-H., Falsafi, B., Roy, K., Vijaykumar, T.N.: Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. In: Proc. International Symposium on Low Power Electronics and Design, July, pp. 90–95 (2000)
Parikh, D., Zhang, Y., Sankaranarayanan, K., Skadron, K., Stan, M.: Comparison of State-Preserving vs. Non-State-Preserving Leakage Control in Caches. In: Proc. 2nd Workshop on Duplicating, Deconstructing, and Debunking, June, pp. 14–24 (2003)
Albonesi, D.H.: Selective Cache Ways: On-Demand Cache Resource Allocation. In: Proc. 32nd International Symposium on Microarchitecture, November, pp. 248–259 (1999)
Yang, S.-H., Powell, M., Falsafi, B., Vijaykumar, T.N.: Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. In: Proc. 8th International Symposium on High-Performance Computer Architecture, February, pp. 147–158 (2002)
Yang, S.-H., Powell, M.D., Falsafi, B., Roy, K., Vijaykumar, T.N.: An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. In: Proc. 7th International Symposium on High-Performance Computer Architecture, January, pp. 147–158 (2001)
Sugumar, R.A., Abraham, S.G.: Efficient Simulation of Multiple Cache Configurations using Binomial Trees. Technical Report CSE-TR-111-91, CSE Division, University of Michigan (1991)
Belady, L.A.: A Study of Replacement Algorithms for a Virtual-Storage Computer. IBM Systems Journal 5(2), 78–101 (1966)
Austin, T.: SimpleScalar 4.0 Release Note. http://www.simplescalar.com/
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In: Proc. 27th International Symposium on Computer Architecture, June, pp. 83–94 (2000)
Zhang, Y., Parikh, D., Sankaranarayanan, K., Skadron, K., Stan, M.: HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Technical Report CS-2003-05, University of Virginia Department of Computer Science (March 2003)
Gonzales, R., Horowitz, M.: Energy Dissipation In General Purpose Microprocessors. IEEE Journal of Solid State Circuits 31(9), 1277–1284 (1996)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Geiger, M.J., McKee, S.A., Tyson, G.S. (2007). Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers I. Lecture Notes in Computer Science, vol 4050. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71528-3_5
Download citation
DOI: https://doi.org/10.1007/978-3-540-71528-3_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-71527-6
Online ISBN: 978-3-540-71528-3
eBook Packages: Computer ScienceComputer Science (R0)