Abstract
Hardware/software partitioning of System-on-chip (SoC partitioning) has a significant effect on the cost and performance of the SoC. Given an embedded system specification and an available core library, the goal of low power SoC partitioning is to select appropriate intellectual-property (IP) cores or software components for the SoC, such that the power consumption of the SoC is minimized under price and timing constraints. SoC partitioning is first formulated to the constrained single-pair shortest-path problem in a directed, weighted graph, and then a novel discrete pulse coupled neural network (PCNN) approach is proposed to get the optimal solution. Autowaves in PCNN are designed specially to meet the constraints and find the optimal path in the constructed graph. Experimental results are given to demonstrate the feasibility and effectiveness of the proposed method.
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Chang, Z., Xiong, G. (2007). Hardware/Software Partitioning of Core-Based Systems Using Pulse Coupled Neural Networks. In: Liu, D., Fei, S., Hou, Z., Zhang, H., Sun, C. (eds) Advances in Neural Networks – ISNN 2007. ISNN 2007. Lecture Notes in Computer Science, vol 4493. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72395-0_124
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DOI: https://doi.org/10.1007/978-3-540-72395-0_124
Publisher Name: Springer, Berlin, Heidelberg
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