Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor

Abstract

On-chip trace data contains run-time information of embedded multi-core processors for software debug. Trace data are transferred through special data path and output pins. Scheduling for combining the traffic of multi-source trace data is one of key issues that affect performance of the on-chip trace system. By analyzing features of trace traffic combination, a lazy scheduling algorithm based on the service threshold and the minimum service granularity is proposed. The queue length distribution is constrained by configurable service threshold of each queue, and switching overheads are reduced by lazy scheduling and configurable minimum service granularity. Two metrics of buffer utilizations on overflowing are presented to evaluate the efficacy of queue priority assignment. Simulation results show that the algorithm controls the overflow rate of each queue effectively and utilizes the buffer capacity according to the queues priority assigned sufficiently. The algorithm is realized in Verilog-HDL. Comparing with a leading method, the overflow rate is reduced 30% with additional 2,015um² in area.