Skip to main content
Springer Nature Link
Log in

Releasing and Scheduling of Lots in a Wafer Fab

  • Conference paper
Algorithmic Aspects in Information and Management (AAIM 2007)

Part of the book series: Lecture Notes in Computer Science ((LNISA,volume 4508))

Included in the following conference series:

  • 815 Accesses

Abstract

In this paper, we address the problem of both releasing and scheduling of lots in a wafer fab. In the lot release problem, we determine the number of lots of different products to be released in each period of a planning horizon in order to minimize total tardiness. The problem of the scheduling of lots at various workstations is modeled as a mathematical program for the objective of minimizing the cycle times of the lots and is solved by the Lagrangian relaxation method. Computational results are presented that exhibit that our methodology constantly generates better solutions compared to those obtained by commonly-used dispatching rules.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Uzsoy, R., Lee, C.Y., Martin-Vega, L.: A review of production planning and scheduling models in semiconductor industry – part I: system characteristics, performance evaluation and production planning. IIE Transactions, Scheduling and Logistics 24, 47–61 (1992)

    Google Scholar 

  2. Uzsoy, R., Lee, C.Y., Martin-Vega, L.: A review of production planning and scheduling models in semiconductor industry – part II: shop-floor control. IIE Transactions, Scheduling and Logistics 26, 44–55 (1994)

    Google Scholar 

  3. Hung, Y.F., Leachman, R.C.: A production planning methodology for semiconductor manufacturing based on iterative simulation and linear programming calculations. IEEE Transactions on Semiconductor Manufacturing 9(2), 257–269 (1996)

    Article  Google Scholar 

  4. Lee, Y., Kim, S., Yea, S., Kim, B.: Production planning in a semiconductor wafer fab considering variable cycle times. Computers in Industrial Engineering 33(3), 713–716 (1997)

    Article  Google Scholar 

  5. Golovin, J.J.: A total framework for semiconductor production planning and scheduling. In: Solid State Technology, pp. 167–170 (1986)

    Google Scholar 

  6. Wein, L.: Scheduling semiconductor wafer fabrication. IEEE Transactions on Semiconductor Manufacturing 1(3), 115–129 (1998)

    Article  Google Scholar 

  7. Kim, Y., Kim, J., Lim, S., Jun, H.: Due date based scheduling and control policies in a multi-product semiconductor wafer fabrication facility. IEEE Transactions on Semiconductor Manufacturing 11(1), 155–164 (1998)

    Article  Google Scholar 

  8. Lu, S., Ramaswamy, D., Kumar, P.R.: Efficient scheduling policies to reduce mean and variance of cycle time in semiconductor manufacturing plants. IEEE Transactions on Semiconductor Manufacturing 7(3), 374–388 (1994)

    Article  Google Scholar 

  9. Sarin, C.S., Shikalgar, S., Shenai, V.: Modeling and analysis for the reduction of cycle time at a wafer fab. In: Proceedings of the International Conference on Semiconductor Manufacturing Operational Modeling and Simulation (2001)

    Google Scholar 

  10. Graves, S., Meal, H., Stefek, D., Zeghmi, A.: Scheduling of re-entrant flow shops. Journal of Operations Management 3(4), 197–207 (1983)

    Article  Google Scholar 

  11. Mehta, S.V., Uzsoy, R.: Minimizing total tardiness on a batch processing machine with incompatible job families. IIE Transactions 30, 165–178 (1998)

    Google Scholar 

  12. Pinedo, M.: Scheduling: Theory, Algorithms and Systems. Prentice-Hall, Englewood Cliffs (1995)

    MATH  Google Scholar 

  13. Baker, K.R.: Introduction to Sequencing and Scheduling. John Wiley & Sons, Chichester (1974)

    Google Scholar 

  14. Shenai, V.: Releasing and scheduling of jobs in a wafer fab. Master thesis, Virginia Polytechnic Institute and State University (2003)

    Google Scholar 

  15. Weiss, G.: On optimal draining of re-entrant fluid lines. In: The IMA Volumes in Mathematics and its Applications, Stochastic Newtorks, vol. 71, pp. 91–103 (1995)

    Google Scholar 

  16. Fisher, M.L.: The Lagrangian relaxation method for solving integer programming problems. Management Science 27(1), 1–18 (1981)

    Article  MATH  MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Grado Department of Industrial and Systems Engineering, Virginia Tech, Blacksburg, VA 24061,  

    Subhash C. Sarin, Vinod D. Shenai & Lixin Wang

Authors
  1. Subhash C. Sarin
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Vinod D. Shenai
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Lixin Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Ming-Yang Kao Xiang-Yang Li

Rights and permissions

Reprints and permissions

Copyright information

© 2007 Springer Berlin Heidelberg

About this paper

Cite this paper

Sarin, S.C., Shenai, V.D., Wang, L. (2007). Releasing and Scheduling of Lots in a Wafer Fab. In: Kao, MY., Li, XY. (eds) Algorithmic Aspects in Information and Management. AAIM 2007. Lecture Notes in Computer Science, vol 4508. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72870-2_11

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-72870-2_11

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-72868-9

  • Online ISBN: 978-3-540-72870-2

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics