Abstract
In future nanotechnologies failure densities are predicted to be several orders of magnitude higher than in current CMOS technologies. For such failure densities existing fault tolerance implementations are inadequate. This work presents several principles of building multiple-fault tolerant memory cells and logic gates for circuits affected by high defect densities as well as a first evaluation of the area cost and performance.
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References
Han, J., Jonker, D.: A System Architecture Solution for Unreliable Nanoelectronic Devices. IEEE Transactions on Nanotechnology 1(4) (2002)
Heath, J.R., et al.: A defect-tolerant architecture for nanotechnolog. Science 280, 1716–1731 (1998)
Likharev, K.K.: Single-electron devices and their applications. Proc. IEEE 87, 606–632 (1999)
Heij, C.P., Hadley, P., Mooij, J.E.: Single-electron inverter. Appl. Phys. Lett. 78, 1140–1142 (2001)
Bachtold, A.: Logic circuits with carbon nanotube transistors. Science 294, 1317–1320 (2001)
Huang, Y., et al.: Logic gates and computation from assembled nanowire building blocks. Science 294, 1313–1317 (2001)
Collier, C.P., et al.: Electronically configurable molecular-based logic gates. Science 285, 391–394 (1999)
Collier, C.P., et al.: A [2]catenane-based solid state electronically reconfigurable switch. Science 289, 1172–1175 (2000)
Tseng, G.Y., Ellenbogen, J.C.: Toward nanocomputers. Science 294, 1293–1294 (2001)
Han, J., Jonker, P.: Toward hardware redundant, fault tolerant logic for Nanoeletronics. IEEE Design and Test of Computers (August 2005)
Pierce, W.H.: Failure-Tolerant Computer Design. Academic Press, San Diego (1965)
Tryon, J.G.: Quadded Logic. In: Wilcox, R.H., Mann, W.C. (eds.) Redundancy Techniques for Computing Systems, pp. 205–228. Spartan Books, New York (1962)
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© 2007 Springer-Verlag Berlin Heidelberg
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Anghel, L., Nicolaidis, M. (2007). Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies. In: Sandoval, F., Prieto, A., Cabestany, J., Graña, M. (eds) Computational and Ambient Intelligence. IWANN 2007. Lecture Notes in Computer Science, vol 4507. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73007-1_52
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DOI: https://doi.org/10.1007/978-3-540-73007-1_52
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-73006-4
Online ISBN: 978-3-540-73007-1
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