Abstract
This paper presents an exact reliability analysis of von Neumann multiplexing using majority gates of fan-in Δ = 3, 5, 7, 9, 11, and the corresponding minimum redundancy factors R = 6, 10, 14, 18, 22. Such results are extremely important for a deeper understanding of von Neumann multiplexing (and its variations), especially when considering the expected unreliable behavior of future nano-devices and interconnects. The analysis confirms and augments well-known theoretical results, and is exact as being obtained using exhaustive counting. The extension of the analysis to the device level will allow us to characterize von Neumann multiplexing with respect to device failures for the first time. The results are very timely and are also explaining a strange (non-linear) behavior of von Neuman multiplexing reported two years ago (based on extensive Monte Carlo simulations).
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Semiconductor Industry Association (SIA): International Technology Roadmap for Semiconductors (ITRS). Intl. SEMATECH, Austin, TX, USA, Edition 2005 and 2006 Update Available at public.itrs.net
Constantinescu, C.: Trends and challenges in VLSI circuit reliability. IEEE Micro 23, 14–19 (2003)
Beiu, V., Rückert, U., Roy, S., Nyathi, J.: On nanoelectronic architectural challenges and solutions. In: Proc. IEEE Conf. Nanotech. IEEE-NANO’04, Munich, Germany, pp. 628–631 (August 2004), See also Beiu,V., Rückert, U. (eds.): Emerging Brain Inspired Nano Architectures, World Scientific Press, in progress (2007/8)
Likharev, K.K.: Single-electron devices and their applications. Proc. IEEE 87, 606–632 (1999)
Feldkamp, U., Niemeyer, C.M.: Rational design of DNA nanoarchitectures. Angew. Chem. Intl. Ed. 45, 1856–1876 (2006)
Lin, C., Liu, Y., Rinker, S., Yan, H.: DNA tile based self-assembly: Building complex nanoarchitectures. Chem. Phys. Chem. 7, 1641–1647 (2006)
Hutchby, J.A., Bourianoff, G.I., Zhirnov, V.V., Brewer, J.E.: Extending the road beyond CMOS. IEEE Circ. and Dev. Mag. 18, 28–41 (2002)
Waser, R. (ed.): Nanoelectronics and Information Technology. Wiley-VCH, Weinheim (2005)
Nicolić, K., Sadek, A. S., Forshaw, M.: Architectures for reliable computing with unreliable nanodevices. In: Proc. IEEE Conf. Nanotech. IEEE-NANO’01, Maui, HI, USA, pp. 254–259 (October 2001), See also Nikolić, K., Sadek, A.S., Forshaw, M.: Fault-tolerant techniques for nanocomputers. Nanotechnology 13, 357–362 (2002). And also Forshaw, M., Crawley, D., Jonker, P., Han, J., Sotomayor Torres, C.: A review of the status of research and training into architectures for nanoelectronic and nanophotonic systems in the European research area, Tech. Rep. FP6/2002/IST/1 Contract #507519 (July 2004), Available at www.ph.tn.tudelft.nl/People/albert/papers/NanoArchRev_finalV2.pdf
von Neumann, J.: Probabilistic logics and the synthesis of reliable organisms from unreliable components, Lecture Notes, Caltech, Pasadena, CA, USA, January 4–15, 1952. In: Shannon, C.E., McCarthy, J. (eds.) Automata Studies, pp. 43–98. Princeton Univ. Press, Princeton (1956)
Roy, S., Beiu, V.: Majority multiplexing—Economical redundant fault-tolerant designs for nanoarchitectures. IEEE Trans. Nanotech. 4, 441–451 (2005), See also Beiu, V.: Neural inspired architectures for nanoelectronics: Highly reliable, ultra low-power, reconfigurable, asynchronous, Special Session, Neural Info. In: Proc. Sys. NIPS’03, Whistler, Canada (December 2003) Available at www.eecs.wsu.edu/~vbeiu/workshop_nips03/
Sadek, A.S., Nikolić, K., Forshaw, M.: Parallel information and computation with restitution for noise-tolerant nanoscale logic networks. Nanotechnology 15, 192–210 (2004)
Forshaw, M., Nikolić, K., Sadek, A.S.: ANSWERS: Autonomous Nanoelectronic Systems With Extended Replication and Signaling. MEL-ARI #28667, 3rd Year Report (2001), Available at ipga.phys.ucl.ac.uk/research/answers/reports/3rd_year_UCL.pdf
Han, J., Jonker, P.: A system architecture solution for unreliable nanoelectronic devices. IEEE Trans. Nanotech. 1, 201–208 (2002)
Evans, W.S., Schulman, L.J.: On the maximum tolerable noise of k-input gates for reliable computations by formulas. IEEE Trans. Info. Theory 49, 3094–3098 (2003), See also Evans, W.S.: Information theory and noisy computation. PhD dissertation, Tech. Rep. TR-94-057 Intl. Comp. Sci. Inst. ICSI, Berkeley, USA (November 1994), Available at ftp://ftp.icsi.berkeley.edu/pub/techreports/1994/tr-94-057.pdf
Gao, J.B., Qi, Y., Fortes, J.A.B.: Bifurcations and fundamental error bounds for fault-tolerant computations. IEEE Trans. Nanotech. 4, 395–402 (2005)
Beiu, V.: The quest for practical redundant computations. In: NSF Workshop on Arch. for Silicon Nanoelectr. and Beyond, Portland State Univ., Portland, OR, USA, unpublished presentation (September 2005), Available at web.cecs.pdx.edu/~strom/beiu.pdf
Beiu, V., Sulieman, M.H.: On practical multiplexing issues. In: Proc. Intl. IEEE Conf. Nanotech. IEEE-NANO’06, Cincinnati, OH, USA, pp. 310–313 (July 2006)
Beiu, V., Ibrahim, W., Alkhawwar, Y.A., Sulieman, M.H.: Gate failures effectively shape multiplexing. In: Proc. Intl. Symp. Defect and Fault Tolerance in VLSI Sys., DFT’06, Washington, DC, USA, pp. 29–35 (October 2006)
Ibrahim, W., Beiu, V., Alkhawwar, Y.A.: On the reliability of four full adder cells. In: Proc. Intl. Design and Test Workshop IDT’06, Dubai, UAE, November 2006 (in press)
Srinivasan, J., Adve, S.V., Bose, P., Rivers, J.A.: Lifetime reliability: Toward and architectural solution. IEEE Micro 25, 2–12 (2005), See also Srinivasan, J.: Lifetime reliability aware microprocessors. PhD dissertation, Dept. CS, Univ. Illinois at Urbana-Champaign, USA (May 2006), Available at rsim.cs.uiuc.edu/Pubs/srinivasan-pdf-thesis.pdf
Beiu, V., Ibrahim, W.: On computing nano-architectures using unreliable nano-devices. In: Lyshevski, S.E. (ed.) Nano and Molecular Electronics Handbook, Francis and Taylor, London (in press, 2007)
Beiu, V.: Limits, challenges, and issues in nano-scale and bio-inspired computing. In: Eshaghian-Wilner, M.M. (ed.): Bio-inspired and Nano-scale Integrated Computing, John Wiley and Sons (in progress, 2007/8)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Beiu, V., Ibrahim, W., Lazarova-Molnar, S. (2007). What von Neumann Did Not Say About Multiplexing Beyond Gate Failures—The Gory Details. In: Sandoval, F., Prieto, A., Cabestany, J., Graña, M. (eds) Computational and Ambient Intelligence. IWANN 2007. Lecture Notes in Computer Science, vol 4507. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73007-1_60
Download citation
DOI: https://doi.org/10.1007/978-3-540-73007-1_60
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-73006-4
Online ISBN: 978-3-540-73007-1
eBook Packages: Computer ScienceComputer Science (R0)