Abstract
Client-side diversification led the video-coding community to develop scalable video-codecs supporting efficient decoding at varying quality levels. This scalability has a lot of advantages but the corresponding decoding algorithm is complex and really stresses the system bandwidth as it replaces the block-based DCT-approach with frame-based wavelets. This has a tremendous impact on the hardware architecture. We present the implementation of the RESUME decoder using reconfigurable hardware designed through the use of state-of-the-art HW/SW-codesign techniques. These techniques were augmented with automatic loop transformations and regression testing. Our efforts resulted in a design capable of decoding more than 25 frames per second at lossless CIF resolution.
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References
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Eeckhaut, H., Devos, H., Faes, P., Christiaens, M., Stroobandt, D. (2007). FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder. In: Vassiliadis, S., Bereković, M., Hämäläinen, T.D. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2007. Lecture Notes in Computer Science, vol 4599. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73625-7_19
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DOI: https://doi.org/10.1007/978-3-540-73625-7_19
Publisher Name: Springer, Berlin, Heidelberg
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