Communication Architecture Simulation on the Virtual Synchronization Framework

Abstract

As multi-processor system-on-chip (MPSoC) has become an effective solution to ever-increasing design complexity of modern embedded systems, fast and accurate HW/SW cosimulation of such system becomes more important to explore wide design space of communication architecture. Recently we have proposed the trace-driven virtual synchronization technique to boost the cosimulation speed while accuracy is almost preserved, where simulation of communication architectures is separated from simulation of the processing components. This paper proposes two methods of simulation modeling of communication architectures in the trace-driven virtual synchronization framework: SystemC modeling and C modeling. SystemC modeling gives better extensibility and accuracy but lower performance than C modeling as confirmed by experimental results. Fast reconfiguration of communication architecture is available in both methods to enable efficient design space exploration.

This work was supported by Brain Korea 21 project, SystemIC 2010 project funded by Korean MOCIE, and Samsung Electronics. This work was also partly sponsored by ETRI SoC Industry Promotion Center, Human Resource Development Project for IT SoC Architect. The ICT and ISRC at Seoul National University and IDEC provide research facilities for this study.