Abstract
While the semiconductor industry has provided us with powerful systems for personal supercomputing, how to efficiently harness the computing power of these systems still remains a major unsolved problem. This challenge must be approached by simultaneously solving the synchronization problem and the parallel programmability problem. This paper reviews the synchronization issues in modern parallel computer architectures, surveys the state of the art approaches used to alleviate these problems, and proposes our Request-Store-Forward (RSF) model of synchronization. This model splits the atomic synchronization operations into two phases, thus freeing the processing elements from polling operations. Finally, we show how we could learn from nature and improve the overall system performance by closely coupling peripheral computing units and functional units.
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Hammond, L., Wong, V., Chen, M., Carlstrom, B.D., Davis, J.D., Hertzberg, B., Prabhu, M.K., Wijaya, H., Kozyrakis, C., Olukotun, K.: Transactional memory coherence and consistency. In: ISCA 31, pp. 102–113 (June 2004)
Herlihy, M., Moss, J.E.B.: Transactional memory: Architectural support for lock-free data structures. In: ISCA 20, 289–300 (May 1993)
Hennessy, J.L., Patterson, D.A.: Computer Architecture-A Quantitative Approach. Morgan Kaufmann, San Francisco (2006)
Yamawaki, A., Iwane, M.: Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. In: Proc. of ISPAN 8 (2005)
Vadlamani, S., Jenks, S.: Architectural Considerations for Efficient Software Execution on Parallel Microprocessors. In: Proc. of IPDPS 21 (2007)
Monchiero, M., Palermo, G., Silvano, C., Villa, O.: An Efficient Synchronization Technique for Multiprocessor Systems on-Chip. ACM SIGARCH Computer Architecture News 34(1) (March 2006)
Zhu, W., Sreedhar, V.C., Hu, Z., Gao, G.R.: Synchronization State Buffer: Supporting Efficient Fine-Grain Synchronization on Many-Core Architectures. In: ISCA, 34 (June 2007)
Kongetira, P., Aingaran, K., Olukotun, K.: A 32-way multithreaded Sparc processor. IEEE Micro., 40–47 (March/April 2005)
Denneau, M., Warren Jr., H.S.: 64-bit Cyclops: Principles of operation (April 2005)
Vangal, S., Howard, J., Ruhl, G., et al.: An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS. In: Procs. of ISSCC 2007 (February 2007)
Held, J., Bautista, J., Koehl, S.: From a Few Cores to Many: A Tera-Scale Computing Research Review, White Paper, Intel Research2006 (2006)
Asanovic, K., Bodik, R., Catanzaro, B.C., Gebis, J.J, Husbands, P., Keutzer, K., Patterson, D.A., Plishker, W.L., Shalf, J., Williams, S.W., Yelick, K.A.: The Landscape of Parallel Computing Research: A View from Berkeley. Technical Report No. UCB/EECS-2006-183 (December 2006)
Kumar, R., Tullsen, D.M., Jouppi, N.P.: Heterogeneous Chip Multiprocessors. Computer, IEEE Computer Society (2005)
Jasionowski, B. J.,Lay, M. K., Margala, M.: A Processor-In-Memory Architecture for Multimedia Compression. IEEE Transaction on VLSI Systems (April 2007)
Sterling, T.L., Zima, H.P.: Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing. ACM/IEEE Supercomputing Conference (2002)
Breach, S.E., Vijaykumar, T.N., Sohi, G.S.: The Anatomy of the Register File in a Multiscalar Processor. In: Proc. MICRO-27 (December 1994)
Keckler, S.W., Dally, W.J., Maskit, D., Carter, N.P., Chang, A., Lee, W.S.: Exploiting Fine-Grain Thread Level Parallelism on the MIT Multi-ALU Processor. In: Proc. 25th ISCA (June 1998)
Kobayashi, R., Iwata, M., Ogawa, Y., Ando, H., Shimada, T.: An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. In: Proc. 25th EUROMICRO (1999)
Lin, W.-Y., Gaudiot, J.-L., Amaral, J.N., Gao, G.R.: Performance Analysis of the I-Structure Software Cache on Multi-Threading Systems. In: IPCCC 2000. Proc. of the 19th IEEE International Performance, Computing, and Communication Conference (February 2000)
Lin, W.-Y., Amaral, J.N., Gaudiot, J.-L., Gao, G.R.: Caching Single-Assignment Structures to Build a Robust Fine-Grain Multi-Threading System. In: IPDPS 2000. Proc. of the 14th International Parallel and Distributed Processing Symposium (May 2000)
Arvind, N.R.S., Pingali, K.K.: I-structures: data structures for parallel computing. ACM Transactions on Programming Languages and Systems (TOPLAS) 11(4), 598–632 (1989)
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Liu, S., Gaudiot, JL. (2007). Synchronization Mechanisms on Modern Multi-core Architectures. In: Choi, L., Paek, Y., Cho, S. (eds) Advances in Computer Systems Architecture. ACSAC 2007. Lecture Notes in Computer Science, vol 4697. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74309-5_28
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DOI: https://doi.org/10.1007/978-3-540-74309-5_28
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74308-8
Online ISBN: 978-3-540-74309-5
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